Skip to main content
SpringerLink
Log in

Noise-Insensitive Digital BIST for any PLL or DLL

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10

Similar content being viewed by others

References

  1. Abidi A (2006) Phase noise and jitter in CMOS ring oscillators. IEEE J Solid-state Circuits 41:1803–1816, Aug

    Article  Google Scholar 

  2. Datasheet for National Semiconductor’s LMK03000

  3. Datasheet for Silicon Labs’ Si550

  4. Jenkins K, Jose A, Heidel D (2005) An on-chip jitter measurement circuit with sub-picosecond resolution. Proceedings of ESSCIRC, pp 157–160

  5. Nose K, Kajita M, Mizuno M (2006) A 1-ps resolution jitter-measurement macro using interpolated jitter oversampling. IEEE J Solid-state Circuits 41:2911–2920, Dec

    Article  Google Scholar 

  6. Sattler S, Oberle D, Eckmueller J (2001) PLL built-in self-test jitter measurement integration into 0.18u CMOS technology. Proceedings of the Test Methods and Reliability of Circuits and Systems Workshop

  7. Sunter S, Roy A (1999) BIST for phase-locked loops in digital applications. Proceedings of the International Test Conference, pp 532–540, Oct

  8. Sunter S, Roy A (2004) On-chip digital jitter measurement, from megahertz to gigahertz. IEEE Des Test Comput 21:314–321, Jul/Aug

    Article  Google Scholar 

  9. Sunter S, Roy A (2005) Structural tests for jitter tolerance in SerDes receivers. Proceedings of the International Test Conference, Oct

  10. Sunter S, Roy A (2007) Purely digital BIST for any PLL or DLL. Proceedings of the European Test Symposium, pp 185–190, May

  11. Sunter S, Roy A U.S. patent 7158899

  12. Tabatabaei S, Ivanov A (2002) Embedded timing analysis: a SoC infrastructure. IEEE Des Test Comput 19(3):22–34, May–June

    Article  Google Scholar 

  13. Taylor K, Nelson B, Chong A, Nguyen H, Lin H, Soma M, Haggag H, Huard J, Braatz J (2004) Experimental results for high-speed jitter measurement technique. Proceedings of the International Test Conference, Oct

  14. Veillette B, Roberts G (1997) On-chip measurement of the jitter transfer function of charge-pump phase-locked loops. Proceedings of the International Test Conference, pp 776–785, Oct

Download references

Author information

Authors and Affiliations

  1. LogicVision (Canada), Inc., 1565 Carling Avenue, Ottawa, ON, Canada, K1Z 8R1

    Stephen Sunter & Aubin Roy

Authors
  1. Stephen Sunter
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Aubin Roy
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Stephen Sunter.

Additional information

Responsible Editor: C. Landrault

Rights and permissions

Reprints and permissions

About this article

Cite this article

Sunter, S., Roy, A. Noise-Insensitive Digital BIST for any PLL or DLL. J Electron Test 24, 461–472 (2008). https://doi.org/10.1007/s10836-007-5061-z

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-007-5061-z

Keywords

Search

Navigation