Abstract
While the cost of silicon drops over years, the IC test cost basically stays flat. Hence, the percentage of the test cost in the overall chip cost increases significantly. For the total test cost, the RF test cost is a major contributor due to its tester requirement as well as the complexity of the RF parametric and functional tests. Design for Test (DFT) is a natural step to take to reduce the overall testing cost when the cost of the silicon to implement many Built-In Self Test (BIST) is virtually negligible. This article presents general guidelines for the RF IC, especially for the System on Chip (SoC) and System in Package (SiP) parts. It discusses the specific guidelines for DFT in order to reduce the RF test cost while still keeping acceptable test quality for both RF parameters and functionalities.
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Acknowledgments
This article is part of Author’s work in Qualcomm, and definitely includes many of co-workers’ effort, such as technical discussions and real implementation. Specifically, author would like to thank Gary Ballandyne at Qualcomm on the subject of quadrature error correction, and Hong Kim on the VCO BIST implementation. Also, Stephan Bar, Ken Montalvo, Michael Back, Toshi Kadota, Angelo Pinto, Jeremy Dunworth, Jeongsik (Paul) Yang, Fred Bossu, Christian Holenstein, Michael Laisne, Karim Arabi and many others helped author on many helpful internal discussions for general DFT topics. Also, I learned a lot from Jochen Rivoir of Verigy, who provided a good basic overview from an outsider’s viewpoint about what RF DFT should be with his proposal to Qualcomm. In the end, I would like to state that this article is based on the on-going team’s effort inside Qualcomm to drive down the total test cost for production with DFT, BIST and other yield enhancement modules.
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Fan, Q. General Design for Test Guidelines for RF IC. J Electron Test 26, 7–12 (2010). https://doi.org/10.1007/s10836-009-5121-7
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DOI: https://doi.org/10.1007/s10836-009-5121-7