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Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer

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Abstract

This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the synchronizer, and HSPICE is used to perform circuit analysis. The major purpose of this analysis is to find all possible faults that might occur in the synchronizer. Simulation results demonstrate that bridging fault effects of the synchronizer depend on fault location, bridging resistance value, the input signal (rising and falling), and the time of input signal application. The issues of bridging fault behavior under the consideration of process variation, and the relationship between bridging faults and the synchronizer failure mechanisms are also discussed.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH, 45221, USA

    Hyoung-Kook Kim & Wen-Ben Jone

  2. SynTest Technologies, Inc., 505 South Pastoria Ave., Suite 101, Sunnyvale, CA, 94086, USA

    Laung-Terng Wang

Authors
  1. Hyoung-Kook Kim
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  2. Wen-Ben Jone
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  3. Laung-Terng Wang
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Corresponding author

Correspondence to Hyoung-Kook Kim.

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Responsible Editor: B. Al-Hashimi

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Kim, HK., Jone, WB. & Wang, LT. Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer. J Electron Test 26, 367–392 (2010). https://doi.org/10.1007/s10836-010-5150-2

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  • DOI: https://doi.org/10.1007/s10836-010-5150-2

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