Skip to main content
Log in

Construction and Analysis of Augmented Time Compactors

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

In this paper, a procedure for constructing time compactors based on a new 3-dimensional augmented product code is presented. Accordingly, augmented time compactors are constructed by assigning a unique triplet <x,y,z> to each scan chain and calculating at least four sets of parity check bits. Parity check bits of each set are XORed into stages of one or more multi-input shift registers. The proposed method allows constructing different classes of time compactors directly based on the coding theory. The constructed augmented time compactors outperform the most advanced time compactors of each respective class. All constructed compactor schemes are strictly defined and establish a clear baseline for future development in this area.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. Bartenstein T, Heaberlin D, Huisman LM, Sliwinski D (2001) Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. In: Proc IEEE International Test Conference, pp 287–296

  2. Benware B, Mrugalski G, Pogiel A, Rajski J, Solecki J, Tyszer J (2010) Diagnosis of failing scan cells through orthogonal response compaction. In: Proc IEEE European Test Symposium, pp 221–226

  3. Cheng W-T, Sharma M, Rinderknecht T, Lai L, Hill C (2006) Signature based diagnosis for logic BIST. In: Proc IEEE International Test Conference, Paper 8.3

  4. Cheng W-T, Tsai K-H, Huang Y, Tamarapalli N, Rajski J (2004) Compactor independent direct diagnosis. In: Proc IEEE Asian Test Symposium, pp 204–209

  5. Chickermane V, Foutz B, Keller B (2004) Channel masking synthesis for efficient on-chip test compression. In: Proc IEEE International Test Conference, pp 452–461

  6. Clouqueur T, Zarrineh K, Saluja KK, Fujiwara H (2005) Design and analysis of multiple weight linear compactors of responses containing unknown values. In: Proc IEEE International Test Conference, pp 1099–1108

  7. Gizdarski E (2008) Constructing augmented multimode compactors. In: Proc IEEE VLSI Test Symposium, pp 29–34

  8. Mazumder P (1993) Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip correcting circuit. In: IEEE Trans Comput 42(12):1453–1467

    Article  Google Scholar 

  9. McCluskey EJ, Burek D, Koenemann B, Mitra S, Patel J, Rajski J, Waicukauski JA (2003) Test data compression. In: IEEE Des Test Comput 20:76–87

    Article  Google Scholar 

  10. Mitra S, Kim KS (2002) X-Compact: An efficient response compaction technique for test cost reduction. In: Proc IEEE International Test Conference, pp. 311–320

  11. Mitra S, Kim KS (2004) X-Compact: an efficient response compaction technique. In: IEEE Trans Comput Aided Des Integr Circ Syst 23(3):421–432

    Article  Google Scholar 

  12. Mitra S, Lumetta SS, Mitzenmacher M (2004) X-tolerant signature analysis. In: Proc International Test Conference, pp 432–441

  13. Mrugalski G, Pogiel A, Rajski J, Tyszer J (2007) Fault diagnosis with convolutional compactors. In: IEEE Trans Comput Aided Des Integr Circ Syst 26(8):1478–1494, August

  14. Naruse M, Porneranz I, Reddy SM, Kundu S (2003) On-chip compression of output responses with unknown values using LFSR reseeding. In: Proc IEEE International Test Conference, pp 1060–1068

  15. Patel JH, Lumetta SS, Reddy SM (2003) Application of Saluja-Karpovsky compactors to test response with many unknowns. In: Proc IEEE VLSI Test Symposium, pp 107–112

  16. Rajski W, Rajski J (2006) Modular compactor of test responses. In: Proc VLSI Test Symposium, pp 242–251

  17. Rajski J, Tyszer J (2005) Synthesis of X-tolerant convolutional compactors. In: Proc IEEE VLSI Test Symposium, pp 114–119

  18. Rajski J, Tyszer J, Mrugalski G, Cheng WT, Mukherjee N, Kassab M (2008) X-Press: two-stage X-tolerant compactor with programmable selector. In: IEEE Trans Comput Aided Des Integr Circ Syst 27(1):147–159

  19. Rajski J, Tyszer J, Wang C, Reddy S (2003) Convolutional compaction of test responses. In: Proc IEEE International Test Conference, pp 745–754

  20. Rajski J, Tyszer J, Wang C, Reddy SM (2005) Finite memory test response compactors for embedded test applications. In: IEEE Trans Comput Aided Des Integr Circ Syst 24(4):622–634

  21. Saluja KK, Karpovsky M (1983) Testing computer hardware through data compression in space and time. In: Proc IEEE International Test Conference, pp 83–88

  22. Savir J, McAnney WH (1988) Identification of failing tests with cycling registers. In: Proc IEEE International Test Conference, pp 322–328

  23. Sharma M, Cheng W-T (2005) X-filter: Filtering unknowns from compacted test responses. In: Proc IEEE International Test Conference, pp 1090–1098

  24. Tang Y, Wunderlich H-J, Vranken H, Hapke F, Wittke M, Engelke P, Polian I, Becker B (2004) X-masking during logic BIST and its impact on defect coverage. In: Proc IEEE International Test Conference, pp 442–451

  25. Touba N (2007) X-canceling MISR – a X-tolerant methodology for compacting output responses with unknown using MISR. In: Proc IEEE International Test Conference, Paper 6.2

  26. Wohl P, Waicukauski JA, Neuveux F, Gizdarski E (2010) Fully X-tolerant, very high scan compression. In: Proc AMC/IEEE Design Automation Conference, pp. 362–367

  27. Wohl P, Waicukauski JA, Patel S, Hay C, Gizdarski E, Mathew B (2005) Hierarchical compactor design for diagnosis in deterministic logic BIST. In: Proc IEEE VLSI Test Symposium, pp 359–365

  28. Wohl P, Waicukauski JA, Patel S, Maston G (2002) Effective diagnosis through interval unloads in a BIST environment. In: AMC/IEEE Design Automation Conference, pp 249–254

  29. Wohl P, Waicukauski JA, Williams TW (2001) Design of compactors for signature-analyzers in built-in self-test. In: Proc IEEE International Test Conference, pp 54–63

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Emil Gizdarski.

Additional information

Responsible Editor: C. Metra

Rights and permissions

Reprints and permissions

About this article

Cite this article

Gizdarski, E. Construction and Analysis of Augmented Time Compactors. J Electron Test 27, 109–122 (2011). https://doi.org/10.1007/s10836-011-5211-1

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5211-1

Keywords

Navigation