Skip to main content
SpringerLink
Log in

Exploring the Limitations of Software-based Techniques in SEE Fault Coverage

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate SEU and SET in microprocessors. A set of well-known rules is presented and implemented automatically to transform an unprotected program into a hardened one. SEU and SET are injected in all sensitive areas of a MIPS-based microprocessor architecture. The efficiency of each rule and a combination of them are tested. Experimental results show the limitations of the control-flow techniques in detecting the majority of SEU and SET faults, even when different basic block sizes are evaluated. A further analysis on the undetected faults with control flow effect is done and five causes are explained. The conclusions may lead designers into developing more efficient techniques to detect these types of faults.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5

Similar content being viewed by others

References

  1. (2005) International Technology Roadmap for Semiconductors: 2005 Edition, Chapter Design, pp 6–7

  2. Alkhalifa Z, Nair VSS, Krishnamurthy N, Abraham JA (1999) Design and evaluation of system-level checks for on-line control flow error detection. In IEEE Trans. on Parallel and Distributed Systems 10(6):627–641. June

  3. Azambuja JR, Sousa F, Rosa L, Kastensmidt FL (2010) The limitations of software signature and basic block sizing in soft error fault coverage. In Proc. of IEEE Latin–American Test Workshop

  4. Azambuja JR, Sousa F, Rosa L, Kastensmidt FL (2010) Evaluating the efficiency of software-only techniques to detect SEU and SET in microprocessors. In Proc. of IEEE Latin American Symposium on Circuits and Systems

  5. Baumann RC (2001) Soft errors in advanced semiconductor devices-part I: the three radiation sources. In IEEE Transactions on Device and Materials Reliability. March

  6. Bolchini C, Miele A, Salice F, Sciuto D (2005) A model of soft error effects in generic ip processors. In Proc. of the 20th IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 334–342

  7. Bolchini C, Pomante L, Salice F, Sciuto D (2005) Reliable system specification for self-checking datapaths. In Proc. of the Conf. on Design, Automation and Test in Europe, pages 1278–1283, Washington, DC, USA. IEEE Computer Society

  8. Cheynet P, Nicolescu B, Velazco R, Rebaudengo M, Sonza Reorda M, Violante M (2000) Experimentally evaluating na automatic approach for generating safety-critical software with respect to transient errors. In IEEE Trans Nucl Sci 47(6 part 3):2231–2236. Dec

    Google Scholar 

  9. Dodd PE, Massengill LW (2003) Basic mechanism and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50:583–602

    Article  Google Scholar 

  10. Goloubeva O, Rebaudengo M, Sonza Reorda M, Violante M (2003) Soft-error detection using control flow assertions. In: Proceedings of the 18th IEEE international symposium on defect and fault tolerance in VLSI systems—DFT 2003, November, pp 581–588

  11. Gorman TJO, Ross JM, Taber AH, Ziegler JF, Muhlfeld HP, Montrose ICJ, Curtis HW, Walsh JL (1996) Field testing for cosmic ray soft errors in semiconductor memories. In IBM Journal of Research and Development, pp 41–49, January

  12. Hangout LMOSS, Jan S (2011) The minimips project. Available online at http://www.opencores.org/projects.cgi/web/minimips/overview

  13. Huang KH, Abraham JA (1984) Algorithm-based fault tolerance for matrix operations. In IEEE Trans Comput 33:518–528. Dec

  14. Lu DJ (1982) Watchdog processors and structural integrity checking. In IEEE Trans. on Computers C-31(7):681–685

  15. Mcfearin LD, Nair VSS (1995) Control-flow checking using assertions. In Proc. of IFIP International Working Conference Dependable Computing for Critical Applications (DCCA-05), Urbana-Champaign, IL, USA, September

  16. Mentor Graphics (2009) http://www.model.com/content/modelsim-support

  17. Nicolescu B, Velazco R (2003) Detecting soft errors by a purely software approach: method, tools and experimental results. In Proc of the Design, Automation and Test in Europe Conference and Exhibition

  18. Oh N, Shirvani PP, McCluskey EJ (2002) Control flow checking by software signatures. In IEEE Trans Reliab 51(2):111–112. (Mar)

    Google Scholar 

  19. Oh N, Shirvani PP, McCluskey EJ (2002) Control-flow checking by software signatures. In IEEE Trans. on Reliability, 51(1):111–122

    Google Scholar 

  20. Oh N, Shirvani E, McCluskey E (2002) Error detection by duplicated instructions in Super-scalar Processors. In IEEE Trans. On Reliability 51–1:63–75

    Google Scholar 

  21. Rebaudengo M, Sonza Reorda M, Torchiano M, Violante M (1999) Soft-error detection through software fault-tolerance techniques. In Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems, pp 210–218

  22. Reis GA, Chang J, Vachharajani N, Rangan R, August DI (2005) SWIFT: software implemented fault tolerance. In Proc. of the Inter. Symp. on Code Generation and Optimization

Download references

Author information

Authors and Affiliations

  1. Instituto de Informática—PPGC—PGMICRO, Universidade Federal do Rio Grande do Sul (UFRGS), Av. Bento Gonçalves 9500, Porto Alegre, RS, Brazil

    José Rodrigo Azambuja, Samuel Pagliarini, Lucas Rosa & Fernanda Lima Kastensmidt

Authors
  1. José Rodrigo Azambuja
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Samuel Pagliarini
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Lucas Rosa
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Fernanda Lima Kastensmidt
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to José Rodrigo Azambuja.

Additional information

Responsible Editor: F. Vargas

A presentation based on this article was made at the Eleventh IEEE Latin-American Test Workshop, Punta del Este, Uruguay, March 28-31, 2010.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Azambuja, J.R., Pagliarini, S., Rosa, L. et al. Exploring the Limitations of Software-based Techniques in SEE Fault Coverage. J Electron Test 27, 541–550 (2011). https://doi.org/10.1007/s10836-011-5218-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-011-5218-7

Keywords

Search

Navigation