Abstract
Testing of three-dimensional (3D) stacked ICs (SICs) is starting to receive considerable attention in the semiconductor industry. Since the die-stacking steps of thinning, alignment, and bonding can introduce defects, there may be a need to test multiple subsequent partial stacks during 3D assembly. We address the problem of test-architecture optimization for 3D stacked ICs to minimize overall test time when either the complete stack only, or the complete stack and multiple partial stacks, need to be tested. A general solution to this problem provides several options for 3D stack testing in a unified framework. We show that optimal test-architecture solutions and test schedules for multiple test insertions are different from their counterparts for a single final stack test. In addition, we present optimization techniques for the testing of TSVs and die-external logic in combination with the dies in the stack.
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This research was supported in part by a Ph.D. Fellowship and contract number 2011-TJ-2118 from the Semiconductor Research Corporation (SRC), and by the National Science Foundation under grant number CCF-1017391.
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Appendix
Appendix
For the sake of completeness, we present the complete ILP models for \(P^{H}_{\rm MTS}\), \(P^S_{\rm MTS}\), and \(P^H_{\rm DTSV,||}\).
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Noia, B., Chakrabarty, K. & Marinissen, E.J. Optimization Methods for Post-Bond Testing of 3D Stacked ICs. J Electron Test 28, 103–120 (2012). https://doi.org/10.1007/s10836-011-5233-8
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DOI: https://doi.org/10.1007/s10836-011-5233-8