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Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

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Abstract

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.

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Authors and Affiliations

  1. Mentor Graphics Corporation, 46871 Bayside Parkway, Fremont, CA, 94538, USA

    Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy, Henrik Hovsepyan & Ara Markosian

  2. Fraunhofer Institute for Non-Destructive Testing, Maria-Reiche-Strasse 2, 01109, Dresden, Germany

    Ehrenfried Zschech & Rene Huebner

Authors
  1. Valeriy Sukharev
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  2. Armen Kteyan
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  3. Jun-Ho Choy
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  4. Henrik Hovsepyan
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  5. Ara Markosian
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  6. Ehrenfried Zschech
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  7. Rene Huebner
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Correspondence to Valeriy Sukharev.

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Responsible Editor: E. J. Marinissen

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Sukharev, V., Kteyan, A., Choy, JH. et al. Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance. J Electron Test 28, 63–72 (2012). https://doi.org/10.1007/s10836-011-5259-y

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  • DOI: https://doi.org/10.1007/s10836-011-5259-y

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