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On the Impact of Performance Faults in Modern Microprocessors

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Abstract

Modern microprocessors incorporate a variety of architectural features, such as branch prediction and speculative execution, which are not critical to the correctness of their operation yet are essential towards improving performance. Accordingly, while faults in the corresponding hardware may not necessarily affect functional correctness, they may, nevertheless, adversely impact performance. In this paper, we investigate quantitatively the performance impact of such faults using a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks. We provide extensive fault simulation-based experimental results that elucidate the various aspects of performance faults and we discuss how this information may guide the inclusion of additional hardware for performance loss recovery and yield enhancement.

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Notes

  1. The instruction cache stores four 32-bit instructions per line, aligned to 16 bytes. However, the first instruction to be fetched in each cycle may not be aligned on a 16-byte boundary. Thus, to guarantee delivery of 4 instructions, two cache lines need to be accessed.

  2. While our performance impact analysis is performed at the RT-Level, we note that a recent study reveals a very strong correlation between the impact of RT-Level and Gate-Level faults on the execution of workload in the IVM processor [25]; hence, we expect that the obtained results are representative of what would be obtained through gate-level fault simulation.

  3. The definitions of architectural state and architectural state corruption used herein are borrowed from [20], where it is stated that “In IVM, Microarchitectural state consists of all the SRAM cells, latches, and flip-flops used to implement a processor microarchitecture. Architectural state is a subset of microarchitectural state defined as the state of the machine that is exposed at the instruction set architecture level (e.g., the program counter, register files, and memory state). So Architectural state corruption is any change in PC, register files, and memory state.”

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Acknowledgments

This work is supported by a generous gift from Intel Corp. The first author performed this research while being a visiting student at Yale University. A preliminary version of parts of the work reported herein was presented at the 2009 International Conference on Computer Design [27]. The authors would like to thank Prof. Sanjay Patel and Nicholas Wang from the University of Illinois at Urbana-Champaign for sharing the IVM microprocessor model and for providing technical assistance in its installation and usage.

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Authors and Affiliations

  1. ECE Department, Polytechnic Institute of New York University, Brooklyn, NY, 11201, USA

    Naghmeh Karimi

  2. ECE Department, New York University, Abu Dhabi, PO Box 129188, Abu Dhabi, UAE

    Michail Maniatakos

  3. SoC Enabling Group, Intel Corporation, Santa Clara, CA, 95050, USA

    Chandrasekharan (Chandra) Tirumurti

  4. EE Department, The University of Texas at Dallas, Richardson, TX, 75080, USA

    Yiorgos Makris

Authors
  1. Naghmeh Karimi
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  2. Michail Maniatakos
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  3. Chandrasekharan (Chandra) Tirumurti
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  4. Yiorgos Makris
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Correspondence to Naghmeh Karimi.

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Responsible Editor: M. Violante

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Karimi, N., Maniatakos, M., Tirumurti, C.(. et al. On the Impact of Performance Faults in Modern Microprocessors. J Electron Test 29, 351–366 (2013). https://doi.org/10.1007/s10836-013-5360-5

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  • DOI: https://doi.org/10.1007/s10836-013-5360-5

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