Abstract
Evaluation of the single event upsets (SEUs) impact on SRAM-based FPGAs is a major issue in the adoption of these FPGAs in aerospace applications. In this context, different approaches have been recorded in the literatures, among which the emulation methods are applied most frequently regarding their proper cost-effectiveness and time-saving aspects. This paper has proposed a new approach for increasing the SEU emulation rate in the dynamic partial reconfiguration (DPR)-based emulators. Unlike the traditional procedure that emulates the SEU faults only in one loop, the proposed three-level management algorithm (3-LMA) consists of three nested loops. Theoretical analysis and experimental results show that the suggested technique is to some orders of magnitude faster than traditional approach.
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Partial support for this research received from ITRC (Iran. Telecommunication Research Center) is gratefully acknowledged.
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Omidi Gosheblagh, R., Mohammadi, K. Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators. J Electron Test 30, 739–749 (2014). https://doi.org/10.1007/s10836-014-5489-x
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DOI: https://doi.org/10.1007/s10836-014-5489-x