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Harzard-Based ATPG for Improving Delay Test Quality

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Abstract

Fault coverage is a popular test criterion in delay testing. In order to improve test coverage, an efficient automatic test pattern generation (ATPG) method especially aimed at hazard-based detection condition (HDC), referred to as HDC test generation, is proposed. The proposed method effectively enhances the testability of the faults which are undetectable under conventional detection conditions (CDC) but may fail the circuit in some special function operations. The necessity and feasibility of the hazard-based detection condition is analyzed. Using the improved traditional stuck-at fault test generation tool, we have implemented an efficient HDC test generation for transition delay fault. Experimental results on ISCAS’89 benchmark circuits demonstrate that the proposed HDC test generation can improve the fault converage by an average of 3.64 % for conventional LOS test and an average of 4.6 % for conventional LOC test.

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Authors and Affiliations

  1. College of management, Hangzhou Dianzi University, Hangzhou, China, 310018

    Tieqiao Liu & Yi Liu

  2. College of Information Science & Engineering, Hunan University, Changsha, China, 410082

    Yingbo Zhou & Shuo Cai

Authors
  1. Tieqiao Liu
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  2. Yingbo Zhou
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  3. Yi Liu
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  4. Shuo Cai
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Corresponding author

Correspondence to Tieqiao Liu.

Additional information

Responsible Editor: A. D. Singh

This paper is partly supported by the National Natural Science Foundation of China (NSFC) under grant No. 61303042 and Zhejiang Provincial Natural Science Foundation of China under grant No. LY14G010006

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Liu, T., Zhou, Y., Liu, Y. et al. Harzard-Based ATPG for Improving Delay Test Quality. J Electron Test 31, 27–34 (2015). https://doi.org/10.1007/s10836-014-5503-3

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  • DOI: https://doi.org/10.1007/s10836-014-5503-3

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