Skip to main content
SpringerLink
Log in

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. Abdul-Aziz M, Tahoori M (2010) Soft error reliability aware placement and routing for FPGAs. In: Proceedings of International Test Conference, pp 1–9

  2. Abramovici M, Stroud C (2001) BIST-based test and diagnosis of FPGA logic blocks. IEEE Trans Very Large Scale Integr Syst 9(1):159–172

    Article  Google Scholar 

  3. Altera Corporation (2003) An analytical review of FPGA logic efficiency in Stratix, Virtex-II, Virtex-II Pro Devices. http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf

  4. Dixon BE (2008) Built-in self-test of the programmable interconnect in field programmable gate arrays. M.S. thesis, Auburn University

  5. Elshafey K (2004) On-line diagnosis of interconnect faults in FPGA-based systems. In: Proceedings of 16th International Conference on Microelectronics, pp 396–399

  6. Farooq U, Marrakchi Z, Mehrez H (2012) FPGA architectures: An overview. In: Tree-based Heterogeneous FPGA Architectures. Springer, New York, pp 7–48

  7. Peng YL, Kwai DM, Chou YF, Wu CW (2014) Application-independent testing of 3-D field programmable gate array interconnect faults. IEEE Trans Very Large Scale Integr Syst 22(2):207–219

    Article  Google Scholar 

  8. Rehman SU, Benabdenbi M, Anghel L (2013) BIST for logic and local interconnect resources in a novel mesh of cluster FPGA. In: Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp 296–301

  9. Rehman SU, Benabdenbi M, Anghel L (2014) Test and diagnosis of FPGA cluster using partial reconfiguration. In: Proceedings of 10th Conference on Ph.D. Research in Microelectronics and Electronics, pp 1–4

  10. Ruan A, Yang J, Wan L, Jie B, Tian Z (2013) Insight into a generic interconnect resource model for xilinx virtex and spartan series FPGAs. IEEE Trans Circ Syst II: Express Briefs 60(11):801–805

    Google Scholar 

  11. Souza CP, De Assis FM, Freire RCS (2010) A new architecture of test response analyzer based on the Berlekamp-Massey Algorithm for BIST. IEEE Trans Instrum Meas 59(12):3168–3173

    Article  Google Scholar 

  12. Stroud C, Wijesuriya S, Hamilton C, Abramovici M (1998) Built-in self-test of FPGA interconnect. In: Proceedings of International Test Conference, pp 404–411

  13. Xilinx Inc (2011) Spartan 3e user guide ug331, xilinx inc. http://www.xilinx.com/support/documentation/user_guides/ug331.pdf

  14. Xilinx Inc (2013) Spartan 3e datasheet ds312. http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf

  15. Yao J, Dixon B, Stroud C, Nelson V (2009) System-level built-in self-test of global routing resources in Virtex-4 FPGAs. In: Proceedings of 41st Southeastern Symposium on System Theory, pp 29–32

Download references

Author information

Authors and Affiliations

  1. Departement of Electrical Engineering, Federal University of Paraíba - UFPB, João Pessoa, Paraíba, Brazil

    Igor Gadelha Pereira, Leonardo Alves Dias & Cleonilson Protásio de Souza

Authors
  1. Igor Gadelha Pereira
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Leonardo Alves Dias
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Cleonilson Protásio de Souza
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Cleonilson Protásio de Souza.

Additional information

Responsible Editor: V. D. Agrawal

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Pereira, I.G., Dias, L.A. & de Souza, C.P. A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis. J Electron Test 31, 207–215 (2015). https://doi.org/10.1007/s10836-015-5515-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-015-5515-7

Keywords

Search

Navigation