Skip to main content
SpringerLink
Log in

A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Soft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical designs. Triple modular redundancy (TMR) is widely used to mask virtually all soft errors but typically incurs high power and area overheads. Therefore, in this paper, a determinate radiation hardened technique for safety-critical CMOS designs is proposed and consists of three hybrid strategies combining gate sizing, supply voltage (V D D ) scaling and threshold voltage (V t h ) scaling to prevent soft errors from occurring. A STA-like method that computes the required pulse width of a transient fault along the propagation path is also developed in this framework. Simulation results show that the proposed technique can effectively eliminate all soft errors on ISCAS’85 circuits and a controller area network bus electrical control unit (CAN-bus ECU) design for automotive electronics when the deposited charges range from 35 fC to 132 fC. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3.3X and 2X, respectively, compared with TMR.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13

Similar content being viewed by others

References

  1. Amusan OA, Massengill LW, Bhuva BL, DasGupta S, Witulski AF, Ahlbin JR (2007) Design techniques to reduce set pulse widths in deep-submicron combinational logic. IEEE Trans Nucl Sci 54(6):2060–2064

    Article  Google Scholar 

  2. Black J, Dodd P, Warren K (2013) Physics of multiple-node charge collection and impacts on single-event characterization and soft error rate prediction. IEEE Trans Nucl Sci 60(3):1836–1851

    Article  Google Scholar 

  3. Carter NP, Naeimi H, Gardner DS (2010) Design techniques for cross-layer resilience. In: Proceedings of the Design, Automation and Test in Europe Conference, pp 1023–1028

  4. Chang AC-C, Huang RH-M, Wen CH-P (2013) CASSER: a closed-form analysis framework for statistical soft error rate. IEEE Trans Very Large Scale Integr Syst 21(10):1837–1848

    Article  Google Scholar 

  5. Choudhury MR, Zhou Q, Mohanram K (2009) Soft error rate reduction using circuit optimization and transient filter insertion. J Electron Test Theory Appl 25:197–207

    Article  Google Scholar 

  6. Dabiri F, Nahapetian A, Massey T, Potkonjak M, Sarrafzadeh M (2008) General methodology for soft-error-aware power optimization using gate sizing. IEEE Trans Comput Aided Des Integr Circ Syst 27(10):1788–1797

    Article  Google Scholar 

  7. DasGupta S, Witulski AF, Bhuva BL, Alles ML, Reed RA, Amusan OA, Ahlbin JR, Schrimpf RD, Massengill LW (2007) Effect of well and substrate potential modulation on single event pulse shape in deep submicron CMOS. IEEE Trans Nucl Sci 54(6):2407–2412

    Article  Google Scholar 

  8. Deogun HS, Sylvester D, Blaauw D (2005) Gate-level mitigation techniques for neutron-induced soft error rate. In: Proceedings of the International Symposium on Quality of Electronic Design, pp 175–180

  9. Dhillon YS, Diril AU, Chatterjee A, Metra C (2005) Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits. In: Proceedings of the International On-Line Testing Symposium, pp 35–40

  10. Dhillon YS, Diril AU, Chatterjee A, Singh AD (2006) Analysis and optimization of nanometer CMOS circuits for soft-error tolerance. IEEE Trans Very Large Scale Integr Syst 14(5):514–524

    Article  Google Scholar 

  11. Ebrahimi M, Asadi H, Tahoori M (2013) A layout-based approach for multiple event transient analysis. In: Proceedings of the Design Automation Conference, pp 1–6

  12. Ferlet-Cavrois V, Massengill LW, Gouker P (2013) “Single event transients in digital CMOS a review. IEEE Trans Nucl Sci 60(3):1767–1790

    Article  Google Scholar 

  13. Garg R, Nagpal C, Khatri SP (2008) A fast, analytical estimator for the seu-induced pulse width in combinational designs. In: Proceedings of the Design Automation Conference, pp 918–923

  14. Harada R, Mitsuyama Y, Hashimoto M, Onoye T (2011) Neutron induced single event multiple transients with voltage scaling and body biasing. In: Proceedings of IEEE International Reliability Physics Symposium, pp 3C.4.1–3C.4.5

  15. Hill EL, Lipasti MH, Saluja KK (2008) An accurate flip-flop selection technique for reducing logic SER. In: Proceedings of the Dependable Systems and Networks, pp 128–136

  16. Ishihara F, Sheikh F, Nikolic B (2004) Level conversion for dual-supply systems. IEEE Trans Very Large Scale Integr Syst 12(2):185–195

    Article  Google Scholar 

  17. Krishnaswamy S, Plaza SM, Markov IL, Hayes JP (2009) Signature-based ser analysis and design of logic circuits. IEEE Trans Computer-Aided Design Integr Circ Syst 28(1):74–86

    Article  Google Scholar 

  18. Limbrick DB, Mahatme NN, Robinson WH, Bhuva BL (2013) Reliability-aware synthesis of combinational logic with minimal performance penalty. IEEE Trans Nucl Sci 60(4):2776–2781

    Article  Google Scholar 

  19. Lyons RE, Vanderkulk W (1962) The sse of triple-modular redundancy to improve computer reliability. IBM J Res Dev 6(2):200–209

    Article  MATH  Google Scholar 

  20. Mahatme NN, Jagannathan S, Loveless TD, Massengill LW, Bhuva BL, Wen S-J, Wong R (2011) Comparison of combinational and sequential error rates for a deep submicron process. IEEE Trans Nucl Sci 58(6):2719–2725

    Article  Google Scholar 

  21. Messenger GC (1982) Collection of charge on junction nodes from ion tracks. IEEE Trans Nucl Sci 29(6):2024–2031

    Article  Google Scholar 

  22. Miskov-Zivanov N, Marculescu D (2006) Mars-C: modeling and reduction of soft errors in combinational circuits. In: Proceedings of the Design Automation Conference, pp 767–772

  23. Miskov-Zivanov N, Marculescu D (2007) Mars-S: modeling and reduction of soft errors in sequential circuits. In: Proceedings of the International Symposium on Quality of Electronic Design, pp 893–898

  24. Miskov-Zivanov N, Wu K-C, Marculescu D (2008) Process variability-aware transient fault modeling and analysis. In: Proceedings of the International Conference on Computer-Aided Design, pp 685–690

  25. Mohanram K, Touba NA (2003) Cost-effective approach for reducing soft error failure rate in logic circuits. In: Proceedings of the International Test Conference, pp 893–901

  26. (2009) Nangate 45nm Open Library, Nangate Inc., http://www.nangate.com/

  27. Narasimham B, Bhuva BL, Schrimpf RD, Massengill LW, Gadlage MJ, Amusan OA, Holman WT, Witulski AF, Robinson WH, Black JD, Benedetto JM, Eaton PH (2007) Characterization of digital single event transient pulse-widths in 130-nm and 90-nm CMOS technologies. IEEE Trans Nucl Sci 54(6):2506–2511

    Article  Google Scholar 

  28. Nicolaidis M (2005) Design for soft error mitigation. IEEE Trans Device Mater Reliab 5(3):405–418

    Article  Google Scholar 

  29. Oklobdzija VG (2007) Digital design and fabrication. CRC-Press

  30. Pagliarini S, Kastensmidt F, Entrena L, Lindoso A, Millan ES (2011) Analyzing the impact of single-event-induced charge sharing in complex circuits. IEEE Trans Nucl Sci 58(6):2768–2775

    Article  Google Scholar 

  31. Quming Z, Mohanram K (2006) Gate sizing to radiation harden combinational logic. IEEE Trans Comput Aided Des Integr Circ Syst 25(1):155–166

    Article  Google Scholar 

  32. Rajaramant R, Kim J, Vijaykrishnan N, Xie Y, Irwin M (2006) Seat-la: a soft error analysis tool for combinational logic. In: Proceedings of the International Conference VLSI Design, pp 499–502

  33. Ramakrishnan K, Rajaramant R, Suresh S, Vijaykrishnan N, Xi Y, Irwin MJ (2007) Variation impact on ser of combinational circuits. In: Proceedings of the International Symposium on Quality Electronic Design, pp 911–916

  34. Rao RR, Blaauw D, Sylvester D (2006) Soft error reduction in combinational logic using gate resizing and flipflop selection. In: Proceedings of the International Conference on Computer-Aided Design, pp 502–509

  35. Rao RR, Chopra K, Blaauw DT, Sylvester DM (2007) Computing the soft error rate of a combinational logic circuit using parameterized descriptors. IEEE Trans Computer-Aided Des Integr Circ Syst 26(3):468–479

    Article  Google Scholar 

  36. Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. In: Proceedings of dependable systems and networks, pp 389–398

  37. Sootkaneung W, Saluja KK (2010) On techniques for handling soft errors in digital circuits. In: Proceedings of the International Test Conference, pp 1–9

  38. Wu K-C, Marculescu D (2014) Power-planning-aware soft error hardening via selective voltage assignment. IEEE Trans Very Large Scale Integr Syst 22(1):136–145

    Article  Google Scholar 

  39. Zhang M, Shanbhag N (2004) A soft error rate analysis (sera) methodology. In: Proceedings of the International Conference Computer Aided Design, pp 111–118

  40. Zhang B, Wang W-S, Orshansky M (2006) Faser: fast analysis of soft error susceptibility for cell-based designs. In: Proceedings of the international symposium on quality electronic design, pp 755–760

Download references

Acknowledgments

This work was particularly supported by National Chip Implementation Center (CIC) and Ministry of Science and Technology (MOST) under contract NSC101-2221-E-009-159-MY3 and MOST103-2220-E-009-014-. We are also grateful to the National Center for High performance Computing (NCHC) for computer time and facilities.

Compliance with Ethical Standards

The authors (Ryan H.-M. Huang, Dennis K.-H. Hsu and Charles H.-P. Wen) declare that they have no conflict of interest. And, this article does not contain any studies with human participants or animals performed by any of the authors. Informed consent was obtained from all individual participants included in the study.

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, National Chiao Tung University, 1001, Ta Hsueh Road, Hsinchu, 300, Taiwan

    Ryan H.-M. Huang, Dennis K.-H. Hsu & Charles H.-P. Wen

Authors
  1. Ryan H.-M. Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Dennis K.-H. Hsu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Charles H.-P. Wen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Ryan H.-M. Huang.

Additional information

Responsible Editor: N. A. Touba

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Huang, R.HM., Hsu, D.KH. & Wen, C.HP. A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs. J Electron Test 31, 181–192 (2015). https://doi.org/10.1007/s10836-015-5517-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-015-5517-5

Keywords

Search

Navigation