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Double Node Upsets Hardened Latch Circuits

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Abstract

A radiation hardened by design (RHBD) latch and its temporally hardened version to tolerate double node upsets are proposed in this paper. C-Elements are used to construct structures for fault correction. The temporally hardened version can further tolerate some single-event transients (SETs) at input port and clock line. Compared with Quintuple Modular Redundancy (QMR), the proposed non-temporally and temporally hardened latches are more area and power efficient with improved propagation delays. Compared with several previously reported temporally hardened latches, the proposed temporally hardened latch may introduce lower performance loss induced as setup time increase. Several multi-node upset tolerant latches are also compared with these two designs in terms of area, power, and delay. A cell level soft error analysis (TFIT) shows that the upset threshold LETs of the proposed latches in 180 nm process are higher than 16 MeV-cm2/mg.

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Acknowledgments

The authors appreciate the supports from CMC Microsystems, iROC Technologies, and NSFC under contract No. 61504038.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada

    Yuanqing Li & Haibin Wang

  2. College of IOT Engineering, Hohai University, Changzhou, China

    Haibin Wang

  3. School of Electronic Information Engineering, Tianjin University, Tianjin, China

    Suying Yao, Xi Yan, Zhiyuan Gao & Jiangtao Xu

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  1. Yuanqing Li
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  2. Haibin Wang
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  3. Suying Yao
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  4. Xi Yan
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  5. Zhiyuan Gao
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  6. Jiangtao Xu
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Correspondence to Yuanqing Li.

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Responsible Editor: S. Hellebrand

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Li, Y., Wang, H., Yao, S. et al. Double Node Upsets Hardened Latch Circuits. J Electron Test 31, 537–548 (2015). https://doi.org/10.1007/s10836-015-5551-3

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  • DOI: https://doi.org/10.1007/s10836-015-5551-3

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