Skip to main content
SpringerLink
Log in

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

A novel SRAM cell tolerant to single-event upsets (SEUs) is presented in this paper. By adding four more transistors inside, the proposed circuit can obtain higher critical charge at each internal node compared to the conventional 6-transistor (6T) cell. Arrays of 2k-bit capacitance of these two designs were implemented in a 65 nm CMOS bulk technology for comparison purpose. Radiation experiments showed that, at the nominal 1.0 V supply voltage, the proposed cell achieves 47.1 % and 49.3 % reduction in alpha and proton soft error rates (SER) with an area overhead of 37 %.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Autran JL, Roche P, Sauze S, Gasiot G, Munteanu D, Loaiza P, Zampaolo M, Borel J (2009) Altitude and underground real-time SER characterization of CMOS 65 nm SRAM. IEEE Trans Nucl Sci 56(4):2258–2266

    Article  Google Scholar 

  2. Bajura MA, Boulghassoul Y, Naseer R, DasGupta S, Witulski AF, Sondeen J, Stansberry SD, Draper J, Massengill LW, Damoulakis JN (2007) Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs. IEEE Trans Nucl Sci 54(4):935–945

    Article  Google Scholar 

  3. Baumann RC (2001) Soft errors in advanced semiconductor devices—part I: the three radiation sources. IEEE Trans Device Mater Rel 1(1):17–22

    Article  Google Scholar 

  4. Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878

    Article  Google Scholar 

  5. Guo J, Xiao L-Y, Mao Z-G (2014) Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology. IEEE Trans Circuits Syst — I: Reg Papers 61(7):1994–2001

    Article  Google Scholar 

  6. Jahinuzzaman SM, Sharifkhani M, Sachdev M (2009) An analytical model for soft error critical charge of nanometric SRAMs. IEEE Trans Very Large Scale Integr (VLSI) Syst. 17(9):1187–1195

    Article  Google Scholar 

  7. Lacoe RC (2008) Improving integrated circuit performance through the application of hardness-by-design methodology. IEEE Trans Nucl Sci 55(4):1903–1925

    Article  Google Scholar 

  8. Lee H-H K, Lilja K, Bounasser M, Relangi P, Linscott I R, Inan U S, Mitra S (2010) LEAP: layout design through error-aware transistor positioning for soft-error resilient sequential cell design. In: Proceedings of the IEEE Int Rel Phys Symp (IRPS), 203–212

  9. Li L, Li Y, Wang H, Liu R, Wu Q, Newton M, Ma Y, Chen L (2015) Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65 nm Technology. J Electron Test 31(5):561–568

    Article  Google Scholar 

  10. Lilja K, Bounasser M, Wen S-J, Wong R, Holst J, Gaspard N, Jagannathan S, Loveless D, Bhuva B (2013) Single-event performance and layout optimization of flip-flops in a 28-nm bulk technology. IEEE Trans Nucl Sci 60(4):2782–2788

    Article  Google Scholar 

  11. Ming Z, Yi X-L, Chang L, Wei Z-J (2011) Reliability of memories protected by multibit error correction codes against MBUs. IEEE Trans Nucl Sci 58(1):289–295

    Article  Google Scholar 

  12. Robust Chip Inc. 2016 Accuro User’s Manual version 8.5

  13. Roche P, Palau JM, Tavernier C, Bruguier G, Ecoffet R, Gasiot J (1999) Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations. IEEE Trans Nucl Sci 46(6):1354–1362

    Article  Google Scholar 

  14. Rodbell KP, Heidel DF, Pellish JA, Marshall PW, Tang HHK, Murray CE, LaBel KA, Gordon MS, Stawiasz KG, Schwank JR, Berg MD, Kim HS, Friendlich MR, Phan AM, Seidleck CM (2011) 32 and 45 nm radiation-hardened-by-design (RHBD) SOI latches. IEEE Trans Nucl Sci 58(6):2702–2710

    Article  Google Scholar 

  15. She X-X, Li N, Jensen DW (2012) SEU tolerant memory using error correction code. IEEE Trans Nucl Sci 59(1):205–210

    Article  Google Scholar 

  16. Torrens G, de Paúl I, Alorda B, Bota S, Segura J (2014) SRAM alpha-SER estimation from word-line voltage margin measurements: design architecture and experimental results. IEEE Trans Nucl Sci 61(4):1849–1855

    Article  Google Scholar 

  17. Wang H-B, Bi J-S, Li M-L, Chen L, Liu R, Li Y-Q, He A-L, Guo G (2014) An area efficient SEU-tolerant latch design. IEEE Trans Nucl Sci 61(6):3660–3666

    Article  Google Scholar 

  18. Weaver HT, Axness CL, McBrayer JD, Browning JS, Fu JS, Ochoa A, Koga R (1987) An SEU tolerant memory cell derived from fundamental studies of SEU mechanisms in SRAM. IEEE Trans Nucl Sci 34(6):1281–1286

    Article  Google Scholar 

  19. Weste NHE, Harris DM (2011) CMOS VLSI design- A circuits and systems perspective. Addison-Wesley, Boston, pp. 75–76

    Google Scholar 

  20. Xie C-M, Wang Z-F, Wang X-H, Wu L-S, Liu Y-B (2011) Novel SEU hardened PD SOI SRAM cell. J Semiconductors 32(11):115017–115015

  21. Zhang G-H, Shao J, Liang F, Bao D-X (2012) A novel single event upset hardened CMOS SRAM cell. IEICE Electronics Express 9(3):140–145

    Article  Google Scholar 

Download references

Acknowledgments

The authors appreciate the supports from the Natural Sciences and Engineering Research Council of Canada (NSERC), CMC Microsystems, ASPIRE (CREATE program), and Robust Chip Inc.

Author information

Author notes

  1. Lixiang Li

    Present address: TSMC Design Technology Canada, Kanata, ON, Canada

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK, Canada

    Yuanqing Li, Li Chen, Rui Liu, Haibin Wang, Michael Newton & Mo Chen

  2. Department of Electrical and Computer Engineering, Dalhousie University, Halifax, NS, Canada

    Lixiang Li & Yuan Ma

  3. College of Information and Control Engineering, China University of Petroleum, Qingdao, China

    Qiong Wu

Authors
  1. Yuanqing Li
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Lixiang Li
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yuan Ma
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Li Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Rui Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

  6. Haibin Wang
    View author publications

    You can also search for this author in PubMed Google Scholar

  7. Qiong Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  8. Michael Newton
    View author publications

    You can also search for this author in PubMed Google Scholar

  9. Mo Chen
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Lixiang Li.

Additional information

Responsible Editor: S. Kajihara

Lixiang Li equally contributed to this work as the first author.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Li, Y., Li, L., Ma, Y. et al. A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets. J Electron Test 32, 137–145 (2016). https://doi.org/10.1007/s10836-016-5573-5

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-016-5573-5

Keywords

Search

Navigation