Abstract
A novel SRAM cell tolerant to single-event upsets (SEUs) is presented in this paper. By adding four more transistors inside, the proposed circuit can obtain higher critical charge at each internal node compared to the conventional 6-transistor (6T) cell. Arrays of 2k-bit capacitance of these two designs were implemented in a 65 nm CMOS bulk technology for comparison purpose. Radiation experiments showed that, at the nominal 1.0 V supply voltage, the proposed cell achieves 47.1 % and 49.3 % reduction in alpha and proton soft error rates (SER) with an area overhead of 37 %.
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The authors appreciate the supports from the Natural Sciences and Engineering Research Council of Canada (NSERC), CMC Microsystems, ASPIRE (CREATE program), and Robust Chip Inc.
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Responsible Editor: S. Kajihara
Lixiang Li equally contributed to this work as the first author.
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Li, Y., Li, L., Ma, Y. et al. A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets. J Electron Test 32, 137–145 (2016). https://doi.org/10.1007/s10836-016-5573-5
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DOI: https://doi.org/10.1007/s10836-016-5573-5