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Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing

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Abstract

In this study, a novel path clustering technique for adaptive path delay testing, where the test paths are altered according to the extracted device parameters, is proposed. The proposed algorithm is based on the k-means++ algorithm. By considering the probability function of the die-to-die systematic process variation, the proposed algorithm clusters path sets to minimize the total number of test paths. A figure of merit for clustering, which represents the expected number of test paths, is also proposed for quantitatively evaluating path clustering under different conditions. The proposed clustering method is evaluated numerically by applying it to the OpenCores benchmark circuit. Using our clustering technique, the average number of test paths in the adaptive test is reduced to less than 92 % compared with those in the conventional test. In addition, adaptive testing using the proposed technique can reduce the test patterns by 94.26 % while retaining the test quality.

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Acknowledgments

This work has been partly supported by JSPS KAKENHI Grant No. 15K15960 and by VDEC, the University of Tokyo, in collaboration with Synopsys, Inc.

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Correspondence to Michihiro Shintani.

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Responsible Editor: K.-J. Lee

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Shintani, M., Uezono, T., Hatayama, K. et al. Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J Electron Test 32, 601–609 (2016). https://doi.org/10.1007/s10836-016-5614-0

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  • DOI: https://doi.org/10.1007/s10836-016-5614-0

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