Skip to main content
SpringerLink
Log in

Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Advances in VLSI technology have made circuits more vulnerable to faults. Architectural vulnerability factor (AVF) reflects the possibility that a transient fault eventually causes an error in the circuit output. This factor represents the system vulnerability to transient faults and is used to compare different fault-tolerant designs or architectures. In this paper, we have introduced a simulation-based fault injection framework which is developed to evaluate the AVF of different adder hardware description models in various abstraction levels. Then, we introduce the most beneficial abstraction level for evaluating the vulnerability of a design. Finally, exploiting our fault injection framework, we compare the inherent fault tolerance of eight famous adders. We have explored the design space of different adder architectures while considering both delay and area constraints for comparing the inherent fault tolerance level of different adder architectures. To the best of our knowledge, this comparative study is not covered in the literature elsewhere.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4

Similar content being viewed by others

References

  1. Alavi SR, Faez K (2007) Fault localization and full error correction in Radix2 signed digit-based adders. In: Proc. of IEEE Pacific rim conference on communications, computers and signal processing (PACRIM), pp. 214–218

  2. Azarpeyvand A, Salehi ME, Firouzi F, Yazdanbakhsh A, Fakhraie SM (2010) Instruction reliability analysis for embedded processors, in Proc. of IEEE 13th international symposium on design and diagnostics of Electronic Circuits & Systems (DDECS), pp. 20-23

  3. Azarpeyvand A, Salehi ME, Fakhraie SM (2012) CIVA: custom instruction vulnerability analysis framework, in Proc. of IEEE 15th international symposium on design and diagnostics of Electronic Circuits & Systems (DDECS), pp. 318-323

  4. Azarpeyvand A, Salehi ME, Fakhraie SM (2012) Vulnerability analysis for custom instructions, In: Proc. of 15th Euromicro conference on digital system design (DSD), pp. 144–147

  5. Azarpeyvand A, Salehi ME, Fakhraie SM (2014) An analytical method for reliability aware instruction set extension. J Supercomput 67(1):104–130

    Article  Google Scholar 

  6. Baraza JC, Gracia J, Gil D, Gil PJ (2000) A prototype of a VHDL-based fault injection tool. In: Proc. of IEEE international symposium on defect and fault tolerance in VLSI systems, pp. 396–404

  7. Bose A, Hasan Babu HM (2015) Optimized designs of reversible fault tolerant BCD adder and fault tolerant reversible carry skip BCD adder, in Proc. of 18th International Conference on Computer and Information Technology (ICCIT), pp. 202–207

  8. Cardarilli GC, Ottavi M, Pontarelli S, Re M, Salsano A (2006) Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders. IEEE Transon Computer 55(11):534–540

    Article  Google Scholar 

  9. Cucu Laurenciu N, Gupta T, Savin V, Cotofana SD (2016) Error correction code protected data processing units, In: Proc. of IEEE/ACM international symposium on nanoscale architectures (NANOARCH), pp. 37–42

  10. Ghosh S, Ndai P, Roy K (2008) A novel low overhead fault tolerant Kogge-stone adder using adaptive clocking. In: Proc. of design, automation and test in Europe (DATE), pp. 366–371

  11. Tahir JM, Dlay SS, Naguib RNG, Hinton OR (1995) Fault tolerant arithmetic unit using duplication and residue codes. Integr VLSI J 18:187–200

    Article  MATH  Google Scholar 

  12. Khedhiri C, Karmani M, Hamdi B, Ka Lok Man (2011) Concurrent error detection adder based on two paths output computation. In: Proc. of Ninth IEEE International Symposium on Parallel and Distributed Processing with Applications Workshops (ISPAW), pp. 27–32

  13. Koren I, Krishna CM (2007) Fault-Tolerant Systems. Morgan-Kaufman, San Francisco

    MATH  Google Scholar 

  14. Kumar P, Sharma RK (2017) Double fault tolerant full adder design using fault localization, in Proc. of international conference on Computational Intelligence & Communication Technology (CICT), pp. 1-6

  15. Mahalakshmi N, Banupriya P (2016) An efficient constant multiplier architecture with error correction codes, in Proc. of international conference on advanced communication control and computing technologies (ICACCCT), pp. 97–100

  16. Mesquita E, Franck H, Agostini L, Guntzel JL (2007) Soft error tolerant carry-select adders implemented into Altera FPGAs, In: Proc. of 3rd southern conference on programmable logic (SPL), pp. 199–202

  17. Mukherjee S, Weaver C, Emer J, Reinhardt S, Austin T (2003) A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, In: Proc. of MICRO

  18. Namazi A, Sedaghat Y, Miremadi SG, Ejlali A (2009) A low-cost fault-tolerant technique for CLA. In: Proc. of 15th IEEE international on-line testing symposium (IOLTS), pp. 217–222

  19. Namazi A, Miremadi SG, Ejlali A (2009) A high speed and low cost error correction technique for the carry select adder, In: Proc. of international conference on availability, reliability and security (ARES), pp. 635–640

  20. Ocheretnij V, Marienfeld D, Sogomonyan ES, Gossel M (2004) Self-checking code-disjoint carry-select adder with low area overhead by use of add1-circuits. In: Proc. of 10th IEEE international on-line testing symposium (IOLTS), pp. 31–36

  21. Oikonomakos P, Fox P (2006) Error correction in arithmetic operations by I/O inversion, In: Proc. of 12th IEEE international on-line testing symposium (IOLTS), pp. 287–292

  22. D.K. Pradhan, Fault-tolerant carry-save adders, in IEEE Transactions on Computers, C-23, 1320–1322, 1974

  23. Rao W, Orailoglu A (2008) Towards fault tolerant parallel prefix adders in nanoelectronic systems, In: Proc. of design, automation and test in Europe (DATE), pp. 360–365

  24. Shanil Mohamed N, Siby TY (2014) 16-bit velocious fault lenient parallel prefix adder, In: Proc. international conference on electronics, communication and computational engineering (ICECCE), pp. 8–11

  25. Townsend WJ et al. (2003) Quadruple time redundancy adders [error correcting adder], In: Proc. of 18th IEEE international symposium on defect and fault tolerance in VLSI systems, pp. 250–256

  26. Zhang Y, Chakrabarty K, Swaminathan V (2003) Energy-aware fault tolerance in fixed-priority real-time embedded systems, In: Proc. of international conference on computer aided design (ICCAD), pp. 209

Download references

Acknowledgments

This research was supported by a grant from Faculty of Computer and Information Technology Engineering, Qazvin Branch, Islamic Azad University.

Author information

Authors and Affiliations

  1. Faculty of Computer and Information Technology Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran

    Mostafa Salehi & Armin Hajaboutalebi Aboutalebi

  2. Department of Electrical and Computer Engineering, University of Zanjan, University Blvd, Zanjan, 45371-38791, Islamic Republic of Iran

    Ali Azarpeyvand

Authors
  1. Mostafa Salehi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ali Azarpeyvand
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Armin Hajaboutalebi Aboutalebi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Mostafa Salehi.

Additional information

Responsible Editor: C. A. Papachristou

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Salehi, M., Azarpeyvand, A. & Aboutalebi, A.H. Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints. J Electron Test 34, 7–14 (2018). https://doi.org/10.1007/s10836-017-5701-x

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-017-5701-x

Keywords

Search

Navigation