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Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

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Abstract

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.

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References

  1. Agarwal VK, Fung ASF (1981) Multiple fault testing of large circuits by single fault test sets. Proc IEEE Trans Comput C-30(11):855–865

    Article  Google Scholar 

  2. Agrawal A, Saldanha A, Lavagno L, Sangiovanni-Vincentelli AL (1996) Compact and complete test set generation for multiple stuck-faults. In: Proceedings computer-Aided design(ICCAD), pp 212–219

  3. Becker B (1992) Synthesis for Testability: Binary Decision Diagrams. In: Finkel A, Jantzen M (eds) STACS 1992. Lecture notes in computer science, vol 577. Springer, Berlin

  4. Berkeley Logic Synthesis and Verification Group, ABC: A System for Sequential Synthesis and Verification, http://www.eecs.berkeley.edu/alanmi/abc/

  5. Dreschler N, Hilgemier M, Fey G, Dreschler R (2004) Disjoint sum of product minimization by evolutionary algorithms, chapter applications of evolutionary computing. Lect Notes Comput Sci 3005:198–207

    Article  Google Scholar 

  6. Dreschler R, Shi J, Fey G (2004) Synthesis of fully testable circuits from BDDs. Proc IEEE Trans Comput Aided Des Integr Circuits Syst 23(3):1–4

    Article  Google Scholar 

  7. Fujita M, Mishenko A (2014) Efficient SAT-based ATPG techniques for all multiple Stuck-At faults. In: Proceedings IEEE international test conference(ITC), pp 1–10

  8. Hayes JP (1971) A NAND model for fault diagnosis in combinational logic networks. Proc IEEE Trans Comput C-20(12):1496–1506

    Article  MathSciNet  MATH  Google Scholar 

  9. Hughes JLA (1988) Multiple fault detection using single fault test sets. Proc IEEE Trans Comput Aided Des 7(1):100–108

    Article  Google Scholar 

  10. Hughes JLA, McCluskey EJ (1984) An analysis of the multiple fault detection capabilites of single Stuck-At fault test sets. In: Proceedings international test conference (ITC), pp 52–58

  11. Jacob J, Biswas NN (1987) GTBD Faults and lower bounds on multiple fault coverage of single fault test sets. In: Proceedings international test conference, pp 849–855

  12. Kim YC, Agrawal VD, Saluja KK (2002) Multiple faults: modeling, simulation and Test. In: Proceedings international conference on VLSI design, pp 592–597

  13. Kohavi I, Kohavi Z (1972) Detection of multiple faults in combinational logic networks. IEEE Trans Comput C-21(6): 556–568. https://doi.org/10.1109/TC.1972.5009008. ISSN: 0018- 9340

    Article  MATH  Google Scholar 

  14. Matrosova A, Nikolaeva E, Kudin D, Singh V (2012) PDF testability of circuits derived by special covering ROBDDs with gates. In: Proceedings East-west design and test symposium, pp 1–5, Kharkov

  15. McCluskey EJ (1984) Verification testing-a pseudoexhaustive test technique. IEEE Trans Comput C-33 (6):541–546. https://doi.org/10.1109/TC.1984.1676477. ISSN: 0018-9340

    Article  MATH  Google Scholar 

  16. McCluskey EJ, Bozorgui-Nesbat S (1981) Design for autonomous test. IEEE Trans Comput C-30(11):866–875. https://doi.org/10.1109/TC.1981.1675717 . ISSN: 0018-9340

    Article  Google Scholar 

  17. Schertz DR, Metze G (1972) A new representation for faults in combinational digital circuits. Proc IEEE Trans Comput C-21(8):858–866

    Article  MATH  Google Scholar 

  18. Shah T, Matrosova A, Singh V (2016) ROBDD based Path Delay Fault Testable Combinational Circuit Synthesis. In: Proceedings East West design and test symposium (EWDTS)

  19. Shah T, Matrosova A, Singh V (2017) Test pattern generation to detect multiple faults in ROBDD based combinational circuits. In: Proceedings IEEE international symposium on on-line testing and robust system design (IOLTS

  20. Shah T, Matrosova A, Kumar B, Fujita M, Singh V (2017) Testing multiple stuck-at faults of robdd based combinational circuit design. In: Proceedings latin American test symposium (LATS)

  21. Takahashi H, Boateng KO, Saluja KK, Takamatsu Y (2002) On diagnosing multiple Stuck-at faults using multiple and single fault simulation in combinational circuits. Proc IEEE Trans Comput Aided Des Integr Circuits Syst 21(3):362–368

    Article  Google Scholar 

  22. Udell JG Jr, McCluskey EJ (1988) Partial hardware partitioning: a pseudoexhaustive test implementation. In: Proceedings international test conference, p 1000

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Authors and Affiliations

  1. CADSL, Department of Electrical Engineering, Indian Institute of Technology Bombay, Main Gate Road, Powai, Mumbai, Maharashtra, 400076, India

    Toral Shah

  2. Department of Applied Mathematics and Cybernatics, Tomsk State University, Lenin Ave, 36, Tomsk, Tomskaya oblast’, 634050, Russia

    Anzhela Matrosova

  3. VLSI Design and Education Center, University of Tokyo, 7 Chome-3-1 Hongo, Bunkyo, Tokyo, 113-8654, Japan

    Masahiro Fujita

  4. Virendra Singh, CADSL, Department of Electrical Engineering, Indian Institute of Technology Bombay, Main Gate Road, Powai, Mumbai, Maharashtra, 400076, India

    Virendra Singh

Authors
  1. Toral Shah
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  2. Anzhela Matrosova
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  3. Masahiro Fujita
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  4. Virendra Singh
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Correspondence to Toral Shah.

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Responsible Editor: L. M. Bolzani Pöhls

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Shah, T., Matrosova, A., Fujita, M. et al. Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J Electron Test 34, 53–65 (2018). https://doi.org/10.1007/s10836-018-5703-3

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  • DOI: https://doi.org/10.1007/s10836-018-5703-3

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