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A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip

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Abstract

Networks-on-chip (NoC) provide the communication infrastructure for high-speed and large-scale computation that integrates several IP-cores on a single die. Faults on network channels severely degrade system performance and throughput. This paper presents a distributed and online mechanism for detecting and locating stuck-at faults (SAFs) in NoC channels. We also study the effects of such faults on various network performance metrics. The inherent parallelism present in the architecture is utilized to design a scheduling scheme that reduces the overall test time and overhead significantly. The proposed test solution scales well with network size, channel width, and network topology. Hardware synthesis based on FPGA shows that it needs small area overhead and low test time compared to prior approaches. Furthermore, it improves packet latency and reduces energy consumption.

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Notes

  1. In a test iteration either the nodes on an odd/even diagonal level execute the 1-step algorithm only. This node selection is comparable to a coin tossing that results in either head/tail mark where appearance of head results in selection of nodes at an odd diagonal level. On the contrary, nodes on an even diagonal level may be selected on the appearance of tail. The diagonal model (D-Model) and Toss-Model are interchangeable used in the rest of the paper.

  2. The labels R1, R2 in this figure and later part of the paper represent TR=I, TR=II, respectively.

References

  1. Agrawal M, Chakrabarty K (2014) Test-time optimization in noc-based manycore socs using multicast routing. In: Proceedings of the 2014 IEEE 32nd VLSI test symposium (VTS), pp 1–6

  2. Aisopos K, DeOrio A, Peh LS, Bertacco V (2011) Ariadne: agnostic reconfiguration in a disconnected network environment. In: Proceedings of the international conference on parallel architectures and compilation techniques, pp 298–309

  3. Alaghi A, Karimi N, Sedghi M, Navabi Z (2007) Online noc switch fault detection and diagnosis using a high level fault model. In: Proceedings of the 22nd IEEE international symposium on defect and fault-tolerance in VLSI systems (DFT), pp 21–29

  4. Amory A, Briao E, Cota E, Lubaszewski M, Moraes F (2005) A scalable test strategy for network-on-chip routers. In: Proceedings of the 2005 IEEE international test conference, pp 9–599

  5. Avresky DR, Shurbanov V, Horst RW, Mehra P (1999) Performance evaluation of the servernet r san under self-similar traffic. In: Proceedings of the 13th international symposium on parallel processing and the 10th symposium on parallel and distributed processing, IPPS’99/SPDP’99 . IEEE Computer Society, Washington, pp 143–147

  6. Babaei S, Mansouri M, Aghaei B, Khadem-Zadeh A (2011) Online-structural testing of routers in network on chip. World Appl Sci J 14(9):1374–1383

    Google Scholar 

  7. Bertozzi D, Benini L (2004) Xpipes: a network-on-chip architecture for gigascale systems-on-chip. IEEE Circuits Syst Mag 4(2):18–31

    Article  Google Scholar 

  8. Bhowmik B, Biswas S, Deka JK (2015) A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects. In: Proceedings of the IEEE 23rd mediterranean conference on control and automation (MED), pp 176–183

  9. Bhowmik B, Biswas S, Deka JK (2016) An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant nocs. In: Proceedings of the IEEE 22nd international symposium on on-line testing and robust system design (IOLTS), pp 195–198

  10. Bhowmik B, Biswas S, Deka JK, Bhattacharya BB (2018) Reliability-aware test methodology for detecting short-channel faults in on-chip networks. IEEE Trans Very Large Scale Integr VLSI Syst 26(6):1–14

    Article  Google Scholar 

  11. Bhowmik B, Deka JK, Biswas S (2015) An odd-even model for diagnosis of shorts on noc interconnects. In: Proceedings of the IEEE 12th India conference (INDICON), pp 1–6

  12. Bhowmik B, Deka JK, Biswas S (2017) A time-optimized scheme towards analysis of channel-shorts in on-chip networks. J Elect Test 33:227–254

    Article  Google Scholar 

  13. Bhowmik B, Deka JK, Biswas S, Bhattacharya BB (2016) On-line detection and diagnosis of stuck-at faults in channels of noc-based systems. In: Proceedings of the IEEE 29th international conference on systems, man, and cybernetics (SMC), pp 4567–4572

  14. Bhowmik BR (2012) Design and analysis of algorithms, 2nd edn. Katson, New Delhi

    MATH  Google Scholar 

  15. Borkar S (2004) Microarchitecture and design challenges for gigascale integration. In: Proceedings of the 37th annual IEEE/ ACM international symposium on microarchitecture, MICRO 37. IEEE Computer Society, Washington, pp 3–3

  16. Carloni L, Pande P, Xie Y (2009) Networks-on-chip in emerging interconnect paradigms: advantages and challenges. In: Proceedings of the 3rd ACM/IEEE 2009 international symposium on networks-on-chip (NoCS 2009), pp 93–102

  17. Caselli N, Strano A, Ludovici D, Bertozzi D (2012) Cooperative built-in self-testing and self-diagnosis of noc bisynchronous channels. In: Proceedings of the IEEE 6th international symposium on embedded multicore socs (MCSoC), pp 159–166

  18. Catania V, Mineo A, Monteleone S, Palesi M, Patti D (2016) Cycle-accurate network on chip simulation with Noxim. ACM Trans Model Comput Simul 27:4:1–4:25

    Article  Google Scholar 

  19. Chatterjee N, Paul S, Chattopadhyay S (2017) Fault-tolerant dynamic task mapping and scheduling for network-on-chip-based multicore platform. ACM Trans Embed Comput Syst 16:108:1–108:24

    Google Scholar 

  20. Chen C, Lu Y, Cotofana S (2012) A novel flit serialization strategy to utilize partially faulty links in networks-on-chip. In: Proceedings of the sixth IEEE/ACM international symposium on networks on chip (NoCS), pp 124–131

  21. Chittamuru SVR, Desai S, Pasricha S (2017) Swiftnoc: a reconfigurable silicon-photonic network with multicast-enabled channel sharing for multicore architectures. J Emerg Technol Comput Syst 13:58:1–58:27

    Article  Google Scholar 

  22. Chung H, Teuscher C (2013) Design and analysis of heterogeneous nanoscale on-chip communication networks. Nano Commun Net 4(1):23–42

    Article  Google Scholar 

  23. Cota E, Kastensmidt F, Cassel M, Herve M, Almeida P, Meirelles P, Amory A, Lubaszewski M (2008) A high-fault-coverage approach for the test of data, control and handshake interconnects in mesh networks-on-chip. Comput IEEE Transact on 57:1202–1215

    Article  MathSciNet  MATH  Google Scholar 

  24. Dai Z, Zhu J (2012) Saturating the transceiver bandwidth: switch fabric design on FPGAs. In: Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays, pp 67–76

  25. Feng C, Lu Z, Jantsch A, Zhang M, Xing Z (2013) Addressing transient and permanent faults in noc with efficient fault-tolerant deflection router. IEEE Trans Very Large Scale Integr Syst 21:1053–1066

    Article  Google Scholar 

  26. Gebali F, Elmiligi H, El-Kharashi MW (2009) Networks-on-chips: theory and practice, 1st edn. CRC Press, Inc., Boca Raton

    MATH  Google Scholar 

  27. Georgiadis A-L, Xydis S, Soudris D (2016) Deploying and monitoring hadoop mapreduce analytics on single-chip cloud computer. In: Proceedings of the 7th workshop on parallel programming and run-time management techniques for many-core architectures and the 5th workshop on design tools and architectures for multicore embedded computing platforms, PARMA-DITAM ’16. ACM, New York, pp 25–30

  28. Ghofrani A, Parikh R, Shamshiri S, DeOrio A, Cheng KT, Bertacco V (2012) Comprehensive online defect diagnosis in on-chip networks. In: Proceedings of the IEEE 30th VLSI test symposium (VTS), pp 44–49

  29. Ghoshal B, Manna K, Chattopadhyay S, Sengupta I (2016) In-field test for permanent faults in fifo buffers of noc routers. IEEE Trans Very Large Scale Integr VLSI Syst 24(1):393–397

    Article  Google Scholar 

  30. Grecu C, Ivanov A, Saleh R, Pande P (2007) Testing network-on-chip communication fabrics. IEEE Trans Comput Aided Des Integr Circuits Syst 26:2201–2214

    Article  Google Scholar 

  31. Hanford N, Ahuja V, Farrens M, Ghosal D, Balman M, Pouyoul E, Tierney B (2016) Improving network performance on multicore systems: Impact of core affinities on high throughput flows. Futur Gener Comput Syst 56:277–283

    Article  Google Scholar 

  32. Herve M, Almeida P, Kastensmidt F, Cota E, Lubaszewski M (2010) Concurrent test of network-on-chip interconnects and routers. In: Proceedings of the 11th Latin American test workshop (LATW), pp 1–6

  33. Herve M, Cota E, Kastensmidt F, Lubaszewski M (2009) Diagnosis of interconnect shorts in mesh nocs. In: Proceedings of the 3rd ACM/IEEE international symposium on networks-on-chip, pp 256–265

  34. Hervé M, Moraes M, Almeida P, Lubaszewski M, Kastensmidt F, Cota R (2011) Functional test of mesh-based nocs with deterministic routing: integrating the test of interconnects and routers. J Electron Test 27 (5):635–646

    Article  Google Scholar 

  35. Huan Y, DeHon A (2012) FPGA optimized packet-switched noc using split and merge primitives. In: Proceedings of the international conference on field-programmable technology, pp 47–52

  36. International Techbology Roadmap for Semiconductors, [Online]: http://www.itrs.net/

  37. Jiang SY, Liang H, Li S, Xie YL, Luo G (2011) A test method of interconnection online detection of noc based on 2d torus topology. In: Proceedings of the 2011 international conference on applied superconductivity and electromagnetic devices, pp 183– 187

  38. Kakoee M, Bertacco V, Benini L (2011) A distributed and topology-agnostic approach for on-line noc testing. In: Proceedings of the 2011 Fifth IEEE/ACM international symposium on networks on chip (NoCS), pp 113–120

  39. Kakoee M, Bertacco V, Benini L (2014) At-speed distributed functional testing to detect logic and delay faults in nocs. IEEE Tran Comput 63(3):703–717

    Article  MathSciNet  MATH  Google Scholar 

  40. Kapre N, Gray J (2015) Hoplite: building austere overlay nocs for fpgas. In: Proceedings of the 25th international conference on field programmable logic and applications (FPL), pp 1–8

  41. Karim F, Nguyen A, Dey S (2002) An interconnect architecture for networking systems on chips. IEEE Micro 22:36–45

    Article  Google Scholar 

  42. Killian C, Tanougast C, Monteiro F, Dandache A (2014) Smart reliable network-on-chip. IEEE Trans Very Large Scale Integr VLSI Syst 22(2):242–255

    Article  Google Scholar 

  43. Liu C, Iyengar V, Pradhan DK (2006) Thermal-aware testing of network-on-chip using multiple-frequency clocking. In: Proceedings of the 24th IEEE VLSI test symposium, pp 6–51

  44. Liu J, Harkin J, Li Y, Maguire L (2015) Low cost fault-tolerant routing algorithm for networks-on-chip. Microprocess Microsyst 39(6):358–372

    Article  Google Scholar 

  45. Maqsood T, Bilal K, Madani SA (2016) Congestion-aware core mapping for network-on-chip based systems using betweenness centrality. Futur Gener Comput Syst

  46. Marinissen E, Arendsen R, Bos G, Dingemanse H, Lousberg M, Wouters C (1998) A structured and scalable mechanism for test access to embedded reusable cores. In: Proceedings of the international test conference, pp 284–293

  47. McPherson JW (2006) Reliability challenges for 45nm and beyond. In: Proceedings of the 43rd annual design automation conference, DAC’06. ACM, New York, pp 176–181

  48. Pande P, Grecu C, Ivanov A, Saleh R, De Micheli G (2005) Design, synthesis, and test of networks on chips. Design Test Comput IEEE 22:404–413

    Article  Google Scholar 

  49. Papamichael MK, Hoe JC (2012) CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. In: Proceedings of the ACM/SIGDA international symposium on field programmable gate arrays, pp 37–46

  50. Qasem MFA, Gu H (2014) Square-octagon interconnection architecture for network-on-chips. In: Proceedings of the IEEE international conference on signal processing, communications and computing (ICSPCC), pp 715–719

  51. Ren P, Meng Q, Ren X, Zheng N (2014) Fault-tolerant routing for on-chip network without using virtual channels. In: Proceedings of the 51st annual design automation conference, DAC’14, pp 102:1–102:6

  52. Reza A, Mirzaee RF (2017) Non-preemptive offline multi-job mapping for a photonic network on a chip. Nano Commun Net 11:11–23

    Article  Google Scholar 

  53. Runge A (2015) FaFNoc: a fault-tolerant and bufferless network-on-chip. Procedia Comput Sci 56:397–402

    Article  Google Scholar 

  54. Runge A (2015) Fault-tolerant network-on-chip based on fault-aware flits and deflection routing. In: Proceedings of the 9th international symposium on networks-on-chip (NOCS), pp 9:1–9:8

  55. Sedghi M, Alaghi A, Koopahi E, Navabi Z (2007) An HDL,-based platform for high level noc switch testing. In: Proceedings of the 16th Asian test symposium, pp 453–458

  56. Shafik R, Mathew J, Pradhan D (2014) Introduction to energy efficient fault tolerant systems. Springer, Berlin

    Book  Google Scholar 

  57. Shafique M, Henkel J (2013) Agent-based distributed power management for kilo-core processors. In: Proceedings of the international conference on computer-aided design, ICCAD ’13. IEEE Press, Piscataway, pp 153–160

  58. Varatkar GV, Marculescu R (2004) On-chip traffic modeling and synthesis for mpeg-2 video applications. IEEE Trans Very Large Scale Integr VLSI Syst 12(1):108–119

    Article  Google Scholar 

  59. Vermeulen B, Dielissen J, Goossens K, Ciordas C (2003) Bringing communication networks on a chip: test and verification implications. IEEE Commun Mag 41:74–81

    Article  Google Scholar 

  60. Wang J, Ebrahimi M, Huang L, Jantsch A, Li G (2015) Design of fault-tolerant and reliable networks-on-chip. In: Proceedings of the IEEE computer society annual symposium on VLSI, pp 545–550

  61. Wang L-T, Wu C-W, Wen X (2006) VLSI Test principles and architectures: design for testability (systems on silicon). Morgan Kaufmann Publishers Inc., San Francisco

    Google Scholar 

  62. Xu J, Wang H, Liu W, Hei X (2013) Towards high-speed real-time http traffic analysis on the tilera many-core platform. In: Proceedings of the IEEE 10th international conference on high performance computing and communications 2013 IEEE international conference on embedded and ubiquitous computing, pp 1763–1768

  63. Ying Zhang FG, Ning W u, Chen X (2014) Novel noc mapping scheme optimized for testing time. In: Proceedings of the world congress on engineering and computer science, pp 1–6

  64. Yu Q, Cano J, Flich J, Ampadu P (2012) Transient and permanent error control for high-end multiprocessor systems-on-chip. In: Proceedings of the sixth IEEE/ACM international symposium on networks on chip (NoCS), pp 169–176

  65. Zeferino C, Kreutz M, Susin A (2004) RASoc: a router soft-core for networks-on-chip. Proc. of the Design, Automation and Test in Europe Conference and Exhibition 3:198–203

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Information Technology, Bhagalpur, 813 210, India

    Biswajit Bhowmik

  2. Department of Computer Science and Engineering, Indian Institute of Technology, Guwahati, 781 039, India

    Santosh Biswas & Jatindra Kumar Deka

  3. Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, 721 302, India

    Bhargab B. Bhattacharya

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  1. Biswajit Bhowmik
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  2. Santosh Biswas
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  4. Bhargab B. Bhattacharya
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Correspondence to Biswajit Bhowmik.

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Bhowmik, B., Biswas, S., Deka, J.K. et al. A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. J Electron Test 35, 215–243 (2019). https://doi.org/10.1007/s10836-019-05792-1

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