Skip to main content
SpringerLink
Log in

An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

Advancements in integrated circuit technologies, increasing manufacturing complexity and incessant device scaling inflict new challenges in memory testing and demand for new, sophisticated test methods. Much research has been devoted to reducing the test time of Data Retention Fault (DRF) using March tests. Recent advancements in research rely on using transient current based tests for fault detection. As the test length of a transient current test is comparatively small when compared to other test methods, the probability of detection of this kind of fault during a test period is very low especially in the case of small memory arrays. Large variations in peak amplitude of voltage and charge may occur due to process variations which limits the detection capability of such tests. The main contribution of this paper is enhancing the detection of DRFs in SRAM using transient current test amidst process variations. In this paper, we implement an innovative approach to SRAM test - wavelet based transient supply current test with modified March sequence exploiting Read Equivalent Stress (RES) for DRF detection. The proposed technique can be merged with transient current test using Built-in-Current Sensors (BICS) resulting in full coverage of DRF. In comparison with other techniques that solely rely on software implementation for fault detection, the proposed technique significantly reduces hardware and performance penalties. Simulation results confirm that compared to other methods the proposed technique can provide high standards of reliability and efficiency in DRF detection.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. Semiconductor industry association (SIA), International technology roadmap for semiconductors (ITRS), 2020, http://www.siaonline.org/home.cfm

  2. Gyepes G, Arbet D, Brenkus J, Stopjakova V, Mihalov J (July 2014) A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays. Microprocess Microsyst 38(5):359–367

    Article  Google Scholar 

  3. Gomez AF, Lavratti F, Medeiros G, Sartori M, Bolzani Poehis L, Champac V, Vargas F (2016) Effectiveness of a hardware-based approach to detect resistive open defects in SRAM cells under process variations. Microelectron Reliab 67:150–158

    Article  Google Scholar 

  4. Kinseher J, Voelker M, Polian I (2017) Improving testability and reliability of advanced SRAM architectures. IEEE Trans Emerg Top Comput:1

  5. L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan, (2003) “Data retention fault in SRAM memories: analysis and detention procedures.”Proc. of 23 rd IEEE VLSI Test Symposium(VTS 05) pp.23–28

  6. Yokoyama H, Tamamoto H, Narita Y (1993) A current testing for CMOS static RAMs. Proc Of International Workshop on Memory Testing:137–142

  7. Kim H-S, Yoon D-H, Kang S (2001) SRAM transparent testing methodology using dynamic power supply current. IEEE Proc Circ Dev Syst 148:217–222

    Article  Google Scholar 

  8. Muhammad K, Amyeen ME, Roy K, Fuchs WK (1998) Fault detection and location using IDD waveform analysis. IEEE Des Test Comput 18:42–49

    Article  Google Scholar 

  9.  Bhunia B, Raychowdhury A, Roy K (2005)  Defect oriented testing of Analog circuits using wavelet analysis of dynamic supply current, Journal of Electronic Testing-Theory and Applications (JETTA), vol. 21: pp. 147-159.

  10. Yu C, Liu G, Lai L (2014) Diagnosis of resistive-open defects using IDDT in digital CMOS circuits, WSEAS Transactions on Circuits and Systems (13):296–300.

  11. Sivamangai MM, Gunavathi K  ( 2011) Fault detection in SRAM cell using wavelet transform based transient current testing method, International Journal of Latest Trends in Software Engineering (IJLTSE) (1): 20–27

  12. P. Princy, N.M. Sivamangai, S. Athira. (2017) An efficient fault detection technique in SRAM using wavelet transform, Proc International Conference on Innovations in Electrical, Electronics, Instrumentation and Media Technology (ICEEIMT) IEEE X-plore, pp -160–165

  13. I. Daubechies, (1992) "Ten lectures on wavelets," CBMS-NSF Regional Conference Series in Applied Mathematics,Society for Industrial and Applied Mathematics, pp. 53–105

  14. Rao R, Bopardikar A (1998) Wavelet transforms: introduction to theory and applications. Addison-Wesley

  15. D. Niggemeyer, M. Redeker and J. Otterstedet, (1998) Integration of non-classical faults in standard march tests, Records of the IEEE Int. Workshop on Memory Technology, Design and Testing, Aug. 1998, pp. 91–96

  16. Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Borri S, Hage-Hassan M (2004) Resistive-open defects in embedded-SRAM core cells: analysis and march test solution. 13th Asian Test Symposium:266–271

  17. Hamdioui S, van de Goor AJ, Rodgers M (2002) March SS – A test for all static simple RAM faults, Proc. of the IEEE International Workshop on Memory Technology,  Design and Testing (MTDT), pp. 95–100

  18. Harutunyan G, Vardanian VA, Zorian Y (2005) Minimal march tests for unlinked static faults in random access memories. Proc of 23rdVLSI Test symposium:53–59

Download references

Author information

Authors and Affiliations

  1. Department. of ECE, Karunya Institute of Technology and Sciences, Coimbatore, Tamil Nadu, India

    Princy P & N.M. Sivamangai

Authors
  1. Princy P
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. N.M. Sivamangai
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Princy P.

Additional information

Responsible Editor: H. Manhaeve

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

P, P., N.M., S. An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM. J Electron Test 35, 473–483 (2019). https://doi.org/10.1007/s10836-019-05819-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-019-05819-7

Keywords

Search

Navigation