Skip to main content
SpringerLink
Log in

Hardware Obfuscation for IP Protection of DSP Applications

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

With an increasing risk of circuit piracy and intellectual property (IP), it is necessary to solve the problem of hardware security in digital signal processing (DSP) via hardware obfuscation. To obscure the circuit at a structural level, a high level of transformation techniques is used. High-level transformations (HLT) not only help in obfuscating the architecture of the circuit, it simultaneously meets the area-speed-power trade-offs. A key-based multiplexer design is proposed for the switch instance, which gives the desired output to the next node only if the configuration key is correct. A single bit change in the key will affect the whole functionality of the design. This key-based multiplexer helps to achieve functional obfuscation. As a result, two-level security is achieved. The objective of this paper is to prevent reverse engineering by structurally and functionally obfuscating the DSP circuit. Implemented and analyzed the area of the obfuscated 3-tap, 5-tap finite impulse response (FIR) filter, and obfuscated infinite impulse response (IIR) filter. Results are compared with those of the non-obfuscated filter circuit. Experimental results show that by applying the high level of transformations, the circuit gets obfuscated. Despite that, the area is reduced. The results confirm that the area of the obfuscated third-order IIR filter design is reduced by 24.56% as compared with its corresponding non-obfuscated filter.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

Data Availability

Not Applicable.

References

  1. Aksoy L et al (2021) "High-level Intellectual Property Obfuscation via Decoy Constants," Proc. IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS). 1–7. https://doi.org/10.1109/IOLTS52814.2021.9486714

  2. Alaql A, Hoque T, Forte D, Bhunia S (2019) "Quality Obfuscation for Error-Tolerant and Adaptive Hardware IP Protection," Proc. IEEE 37th VLSI Test Symposium (VTS). 1–6. https://doi.org/10.1109/VTS.2019.8758637

  3. Alkabani Y, Koushanfar F (2007) “Active Hardware Metering for Intellectual Property Protection and Security.” USENIX Security Symposium 291–306

  4. Amir S, Shakya B, Xiaolin Xu, Jin Y, Bhunia S, Tehranipoor MM, Forte D (2018) Development and Evaluation of Hardware Obfuscation Benchmarks. Journal of Hardware and Systems Security 2:142–161. https://doi.org/10.1007/s41635-018-0036-3

    Article  Google Scholar 

  5. Baluprithviraj KN, Vijayachitra S (2020) Optimization of Logic Obfuscation Technique for Hardware Security. Int J Sci Technol Res 9:1044–1048

    Google Scholar 

  6. Basiri MA, Sk NM (2015) "Configurable Folded IIR Filter Design," in IEEE Transactions on Circuits and Systems II: Express Briefs. 62(12);1144–1148. https://doi.org/10.1109/TCSII.2015.2468917

  7. Bottegal G, Farokhi F, Shames I (2017) "Preserving Privacy of Finite Impulse Response Systems," in IEEE Control Systems Letters. 1(1):128–133. https://doi.org/10.1109/LCSYS.2017.2709621

  8. Chakraborty RS, Bhunia S (2008) “Hardware protection and authentication through netlist level obfuscation,” in Proc. IEEE/ACM International Conference on Computer-Aided Design. 674–677. https://doi.org/10.1109/ICCAD.2008.4681649

  9. Chakraborty RS, Bhunia S (2009) “HARPOON: An obfuscation based SoC design methodology for hardware protection”. IEEE Trans Computer-Aided Design of Integrated Circuits and Sys 28(10):1493–1502. https://doi.org/10.1109/TCAD.2009.2028166

  10. Chang C-H, Cui A (2010) Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property. IEEE Trans Circuits Syst I Regul Pap 57:1618–1630. https://doi.org/10.1109/TCSI.2009.2035415

    Article  MathSciNet  Google Scholar 

  11. Chang CH, Zheng Y, Zhang L (2017) “A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement.” IEEE Circuits and Systems Magazine 17:32–62. https://doi.org/10.1109/MCAS.2017.2713305

  12. Dupuis S, Flottes ML, Di Natale G, Rouzeyre B (2018) "Protection against Hardware Trojans with Logic Testing: Proposed Solutions and Challenges Ahead," in IEEE Design & Test. 35(2):73–90. https://doi.org/10.1109/MDAT.2017.2766170

  13. Guajardo J, Kumar SS, Schrijen GJ, Tuyls P (2008) "Brand and IP protection with physical unclonable functions," Proc. IEEE International Symposium on Circuits and Systems, 3186–3189. https://doi.org/10.1109/ISCAS.2008.4542135

  14. Islam SA, Katkoori S (2018) "High-level synthesis of key based obfuscated RTL data paths". Proc. 19th Int Sym Quality Electr Design (ISQED) 407–412. https://doi.org/10.1109/ISQED.2018.8357321

  15. Lao Y, Parhi KK (2014) "Protecting DSP circuits through obfuscation," Proc.2014 IEEE International Symposium on Circuits and Systems (ISCAS), 798–801. https://doi.org/10.1109/ISCAS.2014.6865256

  16. Lao Y, Parhi KK (2015) "Obfuscating DSP Circuits via High-Level Transformations," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(5):819–830. https://doi.org/10.1109/TVLSI.2014.2323976

  17. Methodology for protection and Licensing of HDL IP by Tarun Batra, Cadence Design Systems, Inc. Noida, India

  18. Naveenkumar R, Sivamangai N. M., Napolean A. and Janani V (2021) "A Survey on Recent Detection Methods of the Hardware Trojans," Proc. 3rd International Conference on Signal Processing and Communication (ICPSC), 139–143. https://doi.org/10.1109/ICSPC51351.2021.9451682

  19. Parhi KK (1989) “Algorithm transformation techniques for concurrent processors,” Proc. IEEE. 77(12);1879–1895. https://doi.org/10.1109/5.48830

  20. Parhi KK (1991) "Pipelining in algorithms with quantizer loops," in IEEE Transactions on Circuits and Systems. 38(7):745–754. https://doi.org/10.1109/31.135746

  21. Parhi KK (1995) High-level algorithm and architecture transformations for DSP synthesis. J VLSI Sig Proc 9:121–143. https://doi.org/10.1007/BF02406474

    Article  Google Scholar 

  22. Parhi KK (2005) "Design of multigigabit multiplexer-loop-based decision feedback equalizers," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13(4):489–493. https://doi.org/10.1109/TVLSI.2004.842935

  23. Parhi KK, Messerschmitt DG (1989) “Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition,” IEEE Transactions on Acoustics, Speech, and Signal Processing. 37(7):1099–1117. https://doi.org/10.1109/29.32286

  24. Parhi KK, Messerschmitt DG(1991) “Static rate-optimal scheduling of iterative data-flow programs via optimum unfolding,” IEEE Transactions on Computers. 40(2):178–195. https://doi.org/10.1109/12.73588

  25. Parhi KK, Wang CY, Brown AP (1992) “Synthesis of control circuits in folded pipelined DSP architectures”. IEEE J Solid-State Circuits 27(1):29–43. https://doi.org/10.1109/4.109555

  26. Roy JA, Koushanfar F, Markov IL (2008) "EPIC: Ending Piracy of Integrated Circuits," Proc. Design, Automation and Test in Europe. 1069–1074. https://doi.org/10.1109/DATE.2008.4484823

  27. Sandeep P, Mennaiah Batta P, Shiva Rama Krishna P, Kiran Kumar D (2020) "Obfuscation Mechanism for DSP Protection”. Int J Eng Res Technol (IJERT) 9(5):6–11. https://doi.org/10.17577/IJERTV9IS050050

  28. Sengupta A, Rathor M (2020) "Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems," in IEEE Transactions on Consumer Electronics, 66(2): 163–172. https://doi.org/10.1109/TCE.2020.2972808

  29. Sengupta A, Rathor M, Patil S, Harishchandra NG (2020) "Securing Hardware Accelerators Using Multi-Key Based Structural Obfuscation," in IEEE Letters of the Computer Society. 3(1);21–24. https://doi.org/10.1109/LOCS.2020.2984747

  30. Shahed QM, Enamul and John A. Chandy, (2019) Key Generation for Hardware Obfuscation Using Strong PUFs. Cryptography 3(3):17. https://doi.org/10.3390/cryptography3030017

    Article  Google Scholar 

  31. Shamsi K, Li M, Plaks K, Fazzari S, Pan DZ, Jin Y (2019) “IP Protection and Supply Chain Security through Logic Obfuscation.” ACM Trans Design Automation of Electronic Sys 24(6):1–36. https://doi.org/10.1145/3342099

  32. Shanbhag NR, Parhi KK (1993) "Relaxed look-ahead pipelined LMS adaptive filters and their application to ADPCM coder," in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 40(12):753–766. https://doi.org/10.1109/82.260240

  33. Suh GE, Devadas S (2007) “Physical Unclonable Functions for Device Authentication and Secret Key Generation.” Proc. 44th ACM/IEEE Design Automation Conf 9–14. https://doi.org/10.1145/1278480.1278484

  34. Sunumol KS, Shanu N (2015) "Obfuscation in DSP algorithms using high level transformations for hardware protection". Proc. IEEE Recent Advs Intelligent Computational Sys (RAICS) 27–32. https://doi.org/10.1109/RAICS.2015.7488383

  35. Vijayakumar A, Patil VC, Holcomb DE, Paar C, Kundu S (2017) "Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques," in IEEE Transactions on Information Forensics and Security. 12(1): 64–77. https://doi.org/10.1109/TIFS.2016.2601067

  36. Wu W, Wang J, Li W, Zhang W (2009) "Design Methods of Multi-DSP Parallel Processing System," Proc. WRI World Congress on Comp Sci Information Eng. 458–464. https://doi.org/10.1109/CSIE.2009.40

  37. Yier J (2015) “Introduction to Hardware Security.” Electronics 4:763–784. https://doi.org/10.3390/electronics4040763

  38. Zhu X, Basten T, Geilen M, Stuijk S (2012) "Efficient Retiming of Multirate DSP Algorithms," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31(6);831–844. https://doi.org/10.1109/TCAD.2011.2182352

  39. Zhuang X, Hsien-Hsin TZ, Lee S, Pande S (2004) “Hardware assisted control flow obfuscation for embedded processors,” in Proc. International Conference on Compilers, Architecture, And Synthesis for Embedded Systems. 292–302. https://doi.org/10.1145/1023833.1023873

Download references

Funding

Nil.

Author information

Authors and Affiliations

  1. Karunya Institute of Technology and Sciences, Coimbatore-641114, Tamilnadu, India

    Naveenkumar R, N.M. Sivamangai & Napolean A

  2. Accenture, Chennai, 600063, Tamilnadu, India

    G. Akashraj Nissi

Authors
  1. Naveenkumar R
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. N.M. Sivamangai
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Napolean A
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. G. Akashraj Nissi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Naveenkumar R.

Ethics declarations

Research Involving Human and Animal Participants

Not Applicable.

Conflict of Interest

Nil.

Additional information

Communicated by C. A. Papachristou

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

R, N., Sivamangai, N., A, N. et al. Hardware Obfuscation for IP Protection of DSP Applications. J Electron Test 38, 9–20 (2022). https://doi.org/10.1007/s10836-022-05984-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-022-05984-2

Keywords

Search

Navigation