Abstract
Semiconductor industry has been one of the most complicated industries driven by Moore’s Law for continuous technology evolution. In order to meet the requirements of high resolution and alignment accuracy, the lithography equipments have been advanced from step-and-repeat system to step-and-scan system. As the tolerance of linewidths is becoming tight and slight, overlay errors must be controlled within the tolerance to maintain the yield. In particular, overlay errors can be compensated by modifying the corresponding equipment setup parameters. However, little research has been done to deal with overlay errors of the step-and-scan system. This study aimed to develop a modeling and decision analysis framework in which the overlay error model for step-and-scan system was constructed and the optimal sampling strategy for measuring and compensating the overlay errors was thus designed. Furthermore, we validated the proposed model and sampling strategy by empirical studies conducted in a fab. We compared the proposed sampling strategy with alternative sampling strategies including the existing sampling strateg based on the model adequacy of R-squares and the model effectiveness of residual errors. The results demonstrated the practical viability of the proposed approach.
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Chien, CF., Hsu, CY. UNISON analysis to model and reduce step-and-scan overlay errors for semiconductor manufacturing. J Intell Manuf 22, 399–412 (2011). https://doi.org/10.1007/s10845-009-0298-2
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DOI: https://doi.org/10.1007/s10845-009-0298-2