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Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption

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Abstract

In this paper, we proposed a novel low power and high-speed FPGA implementation of the 4D memristor chaotic system with cubic nonlinearity based on Xilinx System Generator (XSG) model. Firstly, a pseudo-random number generator based on the proposed XSG FPGA implementation of the proposed 4D memristor chaotic system which implemented into Xilinx Spartan-6 X6SLX45 board with 32 fixed-point format. The aim of the FPGA implementation is increasing the frequency of the memristor chaotic random number generators. The FPGA implementation of the memristor chaotic system results show that the new design approach achieves a maximum frequency of 393 MHz and dissipates 117 m watt. The standard fifteen randomization tests are used to measure the quality of the proposed pseudo-random number generator based on the 4D memristor chaotic system and it gives an excellent randomization analysis. Also, the gray image encryption scheme based on the 4D memristor chaotic system has been introduced. The proposed cryptosystem has a large keyspace, very low correlation values, high entropy which is much closer to the ideal entropy value, a high number of pixels change rate and high unified average changing intensity values. The results and security analysis of the proposed encryption scheme demonstrate that the investigated encryption approach can protect high speed and high security against various attack.

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Authors and Affiliations

  1. Communications and Computer Department, Faculty of Engineering, Delta University for Science and Technology, Gamasa, Mansoura, Egypt

    Esam A. A. Hagras & Mohamed Saber

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  1. Esam A. A. Hagras
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  2. Mohamed Saber
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Correspondence to Esam A. A. Hagras.

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Hagras, E.A.A., Saber, M. Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption. Multimed Tools Appl 79, 23203–23222 (2020). https://doi.org/10.1007/s11042-019-08517-w

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