Abstract
A partitioning methodology between the reconfigurable hardware blocks of different granularity, which are embedded in a generic heterogeneous architecture, is presented. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by a 2-Dimensional Array of Processing Elements. Critical parts, called kernels, are mapped on the coarse-grain reconfigurable logic for improving performance. The partitioning method is mainly composed by three steps: the analysis of the input code, the mapping onto the Coarse-Grain Reconfigurable Array and the mapping onto the FPGA. The partitioning flow is implemented by a prototype software framework. Analytical partitioning experiments, using five real-world applications, show that the execution time speedup relative to an all-FPGA solution ranges from 1.4 to 5.0.
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Galanis, M.D., Dimitroulakos, G. & Goutis, C.E. Partitioning Methodology for Heterogeneous Reconfigurable Functional Units. J Supercomput 38, 17–34 (2006). https://doi.org/10.1007/s11227-006-6743-5
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DOI: https://doi.org/10.1007/s11227-006-6743-5