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Optimizing modulo scheduling to achieve reuse and concurrency for stream processors

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Abstract

Both reuse and concurrency are performance-critical for stream processors. When applying loop unrolling and software pipelining separately to stream-level loops, either reuse or concurrency or both may be inadequately exploited. In this paper, we optimize modulo scheduling to maximize stream reuse and improve concurrency for stream-level loops. The key insight is that an unrolled and software-pipelined stream-level loop could be described by a set of reuse equations. Guided by reuse equations, a reuse-aware modulo scheduling algorithm is developed to simultaneously optimize the two performance objectives, reuse, and concurrency, for a loop in a unified framework. Moreover, we describe a code generation algorithm to automatically produce the optimized loop from a given loop. The experimental results obtained on FT64 and by simulation demonstrate the effectiveness of the proposed approach.

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Authors and Affiliations

  1. School of Computer, National University of Defense Technology, Changsha, 410073, China

    Li Wang & Xuejun Yang

  2. School of Computer Science and Engineering, UNSW, Sydney, NSW, 2052, Australia

    Jingling Xue

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  1. Li Wang
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  2. Jingling Xue
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  3. Xuejun Yang
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Correspondence to Li Wang.

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Wang, L., Xue, J. & Yang, X. Optimizing modulo scheduling to achieve reuse and concurrency for stream processors. J Supercomput 59, 1229–1251 (2012). https://doi.org/10.1007/s11227-010-0522-z

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