Abstract
Multistage interconnection networks (MINs) are widely used for reliable data communication in a tightly coupled large-scale multiprocessor system. High reliability of MINs can be achieved using fault tolerance techniques. The fault tolerance is generally achieved by disjoint paths available through multiple connectivity options. The gamma interconnection network (GIN) is a class of fault tolerant MINs providing alternate paths for source–destination node pairs. Various 2-disjoint and 3-disjoint GIN architectures have been presented in the literature. In this paper, two new designs of 4-disjoint paths multistage interconnection networks, called 4-disjoint gamma interconnection networks (4DGIN-1 and 4DGIN-2) are proposed. The proposed 4DGINs provide four disjoint paths for each source–destination pair and can tolerate three switches/link failures in intermediate interconnection layers. Proposed designs are highly reliable GIN with higher fault-tolerant capability than other gamma networks at low cost. Terminal pair reliabilities of proposed designs and various other 2-disjoint and 3-disjoint GINs are evaluated, analyzed and compared. Reliability values of proposed designs are found higher.
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References
Lawrie DH (1975) Access and alignment of data in an array processor. IEEE Trans Comput 24(12):1154–1155
Pease MC (1977) The indirect binary n-cube microprocessor array. IEEE Trans Comput 26(5):458–473
Lang T, Stone HS (1976) A shuffle-exchange network with simplified control. IEEE Trans Comput 25(1):55–65
Patel JH (1979) Processor-memory interconnection for multiprocessors. In: Proceedings of 6th Annual symposium on computer architecture, pp 168–177
Goke LR, Lipovski GJ (1973) Banyan networks for partitioning multiprocessor systems. In: Proceedings of 6th Annual symposium on computer architecture, pp 21–28
Clos C (1953) A study of non-blocking switching networks. Bell Syst Tech J 32(2):406–424
Nassimi D, Sahni S (1981) A self-routing benes network and parallel permutation algorithms. IEEE Trans Comput 30(5):332–340
Kumar VP, Reddy SM (1987) Augmented shuffle exchange multistage interconnection networks. IEEE Trans Comput 20(6):30–40
Sengupta J, Bansal PK, Gupta A (2000) Permutation and reliability measures of regular and Irregular MINs. In: Proceedings od IEEE TENCON, pp 531–536
Parker DS, Raghavendra CS (1984) The gamma network. IEEE Trans Comput 33(4):367–373
Siegel HJ (1979) Interconnection networks for SIMD machines. IEEE Trans Comput 12(6):57–65
McMillen RJ, Siegel HJ (1982) Performance and fault tolerance improvements in the inverse augmented data manipulator network. 9th Symposium on Computer Architecture, pp 63–72
Lee KY, Yoon H (1989) The PM22I interconnection network. IEEE Trans Comput 38(2):902–907
Lee KY, Hegazy W (1988) The extra stage gamma network. IEEE Trans Comput 37(11):1445–1450
Lee KY, Yoon H (1990) The B-network: a multistage interconnection network with backward links. IEEE Trans Comput 39(7):966–969
Chung CP (1996) CGIN: a fault-tolerant modified gamma interconnection network. IEEE Trans Parallel Distrib Syst 7(12):1301–1306
Chen CW, Chung CP (2001) Fault-tolerant gamma interconnection networks without backtracking. J Syst Softw 58:23–31
Chen CW, Lu NP, Chen TF, Chung CP (2000) Fault-tolerant gamma interconnection networks by chaining. IEEE Proc Comput Digital Tech 147(2):75–80
Seo SW, Feng TY (1995) The composite banyan network. IEEE Trans Parallel Distrib Syst 6(10):1043–1054
Venkatesan R, Mouftah HT (1992) alanced gamma network-A new candidate for broadband packet switch architectures. IEEE INFOCOM, Los Alamitos, pp 2482–2488
Chuang PJ (1994) CGIN: a modified gamma interconnection network with multiple disjoint paths. In: Proceedings of International Conference of Parallel and Distributed Systems, pp 366–372
Chuang PJ (1998) Creating a highly reliable modified gamma interconnection network using a balance approach. IEEE Proc Comput Digital Tech 145(1):27–32
Borkar MA (2011) 3D-CGIN: 3 disjoint paths CGIN with alternate source. Proc Adv Comput Commun 193:25–36
Chen CW, Lu NP, Chen TF, Chung CP (2003) 3-disjoint gamma interconnection networks. J Syst Softw 66:129–134
Chen CW, Chung CP (2005) Designing a disjoint paths interconnection network with fault tolerance and collision solving. J Supercomput 34:63–80
Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor, theoretical properties and algorithms. Parallel Comput 21(11):1783–1805
Arabnia HR, Smith JW (1993) A reconfigurable interconnection network for imaging operations and its implementation using a multi-stage switching box. In: Proceedings of 7th Annual International High Performance Computing Conference, pp 349–357
Aggarwal RR (2012) Design and performance evaluation of a new irregular fault-tolerant multistage interconnection network. Int J Comput Sci Issues 9(2):108–113
Patel JH (1981) Performance of processor-memory interconnections for multiprocessors. IEEE Trans Comput 30(10):771–780
Gunawan I, Fard NS (2012) Terminal reliability assessment of gamma and extra-stage gamma networks. Int J Qual Reliab Manage 29(7):820–831
Chaturvedi SK, Misra KB (2002) An efficient multi-variable inversion algorithm for reliability evaluation of complex systems using path sets. Int J Reliab Qual Saf Eng 9(3):237–259
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Rajkumar, S., Goyal, N.K. Design of 4-disjoint gamma interconnection network layouts and reliability analysis of gamma interconnection Networks. J Supercomput 69, 468–491 (2014). https://doi.org/10.1007/s11227-014-1175-0
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DOI: https://doi.org/10.1007/s11227-014-1175-0