Abstract
Power consumption has become a major design concern in current high-performance chip multiprocessors, and this problem exacerbates with the number of core counts. A significant fraction of the total power budget is often consumed by on-chip caches, thus important research has focused on reducing energy consumption in these structures. To enhance performance, on-chip caches are being deployed with a high associativity degree. Consequently, accessing concurrently all the ways in the cache set is costly in terms of energy. This paper presents the PS-Cache architecture, an energy-efficient cache design that reduces the number of accessed ways without hurting the performance. The PS-Cache takes advantage of the private-shared knowledge of the referenced block to reduce energy by accessing only those ways holding the kind of block looked up. Experimental results show that, on average, the PS-Cache architecture can reduce the dynamic energy consumption of L1 and L2 caches by \(22\) and \(40\,\%\), respectively.
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Notes
Experimental environment, system parameters, protocols and cache hierarchy are described in Section 5.
If a TLB miss occurs, after solving the miss the corresponding entry is in the TLB.
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Acknowledgments
This work has been jointly supported by the MINECO and European Commission (FEDER funds) under the project TIN2012-38341-C04-01 and the Fundaci’on Seneca-Agencia de Ciencia y Tecnolo’ia de la Regi’on de Murcia under the project J’ovenes L’ideres en Investigaci’on 18956/JLI/13.
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Valls, J.J., Ros, A., Sahuquillo, J. et al. PS-Cache: an energy-efficient cache design for chip multiprocessors. J Supercomput 71, 67–86 (2015). https://doi.org/10.1007/s11227-014-1288-5
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DOI: https://doi.org/10.1007/s11227-014-1288-5