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Application mapping algorithms for mesh-based network-on-chip architectures

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Abstract

Due to shrinking technology sizes, more and more processing elements and memory blocks are being integrated on a single die. However, traditional communication infrastructures (e.g., bus or point-to-point) cannot handle the synchronization problems of these large systems. Using network-on-chip (NoC) is a step towards solving this communication problem. Energy- and communication-efficient application mapping is a previously studied problem for mesh-based NoC architectures; however, there is still need for intelligent mapping algorithms since current algorithms either take too much running time or do not determine accurate results. To fill this need, in this study, we propose two mapping algorithms (one based on simulated annealing and one based on genetic algorithm) for energy- and communication-aware mapping problems of mesh-based NoC architectures. We compare these two algorithms with an integer linear programming-based method and a heuristic method using several multimedia and synthetic benchmarks.

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References

  1. Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proc. Design Automation Conference, Las Vegas, pp 684–689

  2. Benini L, De Micheli G (2002) Networks on chips: a new SoC paradigm. IEEE Comput 35(1):70–78

    Article  Google Scholar 

  3. Davis JA, Venkatesan R, Kaloyeros A, Beylansky M, Souri SJ, Banerjee K, Saraswat KC, Rahman A, Reif R, Meindl JD (2001) Interconnect limits on gigascale integration (GSI) in the 21st century. In: Proceeding of the IEEE, vol 89, no 3, pp 305–324

  4. Sylvester D, Keutzer K (2000) A global wiring paradigm for deep submicron design. In: IEEE Transaction on computer-aided design of integrated circuits and systems (CAD/ICAS), vol 19, no 2, pp 242–252

  5. Arabnia HR, Oliver MA (1989) A transputer network for fast operations on digitised images. In: International Journal of Eurographics Association (Computer Graphics Forum), vol 8, no 1, pp 3–12

  6. Arabnia HR (1990) A parallel algorithm for the arbitrary rotation of digitized images using process-and-data-decomposition approach. J Parallel Distrib Comput 10(2):188–193

    Article  Google Scholar 

  7. Bhandarkar SM, Arabnia HR (1995) The REFINE multiprocessor: theoretical properties and algorithms. Parallel Comput J 21(11):1783–1806

    Article  Google Scholar 

  8. Arabnia HR, Smith JW (1993) A reconfigurable interconnection network for imaging operations and its implementation using a multi-stage switching box. In: Proceedings of the 7th Annual International High Performance Computing Conference. The 1993 High Performance Computing: New Horizons Supercomputing Symposium, Calgary, pp 349–357

  9. Suleyman T, Ozcan O, Meltem O (2009) An ILP formulation for application mapping onto network-on-chips. In: 3rd International Conference on Application of Information and Communication Technologies, AICT2009, Baku

  10. Suleyman T (2010) New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs. J Syst Architect. doi:10.1016/j.sysarc.2010.10.001

  11. Murali S, De Micheli (2004) Bandwidth-constrained mapping of cores onto NoC Architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe, vol 2, Washington DC

  12. Janidarmian M, Khademzadeh A, Tavanpour M (2009) Onyx: a new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip. In: IEICE Electron. Express, vol 6, no 1, pp 1–7

  13. Shen W, Chao C, Lien Y, Wu A (2007) A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network. In: Proceedings of the First international Symposium on Networks-on-Chip, Washington DC

  14. Hu J, Marculescu R (2005) Communication and task scheduling of application-specific networks-on-chip. In: Computers and Digital Techniques, IEE Proceedings, vol 152, no 5, pp 643–651

  15. Zhonghai L, Lei X, Axel J (2008) Cluster-based simulated annealing for mapping cores onto 2D mesh networks on chip. In: Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS ’08), IEEE Computer Society, Washington DC

  16. Moein-darbari Fahime, Khademzade Ahmad, Gharooni-fard Golnar (2009) CGMAP:a new approach to network-on-chip mapping problem. IEICE Electron Express 6(1):27–34

    Article  Google Scholar 

  17. Ascia G, Catania V, Palesi (2004) Multi-objective mapping for mesh-based NoC architectures. In: Proceedings of the 2nd IEEE/ACM/IFIP international Conference on Hardware/Software Codesign and System Synthesis, Stockholm

  18. Hung W, Addo-Quaye C, Theocharides T, Xie Y, Vijaykrishnan N, Irwin MJ (2004) Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. Proceedings of the IEEE international Conference on Computer Design (October 11–13, 2004). ICCD. IEEE Computer Society, Washington, DC, pp 430–437

  19. da Silva MVC, Nedjah N, Mourelle LM (2010) Power-aware multiobjective evolutionary optimisation for application mapping on network-on-chip platforms. Int J Electron 97(10):1163–1179

    Article  Google Scholar 

  20. Nedjah N, da Silva MVC, Mourelle LM (2011) Customized computer-aided application mapping on NoC infrastructure using multi-objective optimization. J Syst Archit 57(1):79–94

    Article  Google Scholar 

  21. Nedjah N, da Silva MVC, Mourelle LM (2012) Preference-based multi-objective evolutionary algorithms for power-aware application mapping on NoC platforms. Expert Syst Appl 39(3):2771–2782

    Article  Google Scholar 

  22. Srinivasan K, Chatha, KS (2005) A technique for low energy mapping and routing in network-on-chip architectures. In: Proceedings of the 2005 international Symposium on low power electronics and design (San Diego, CA, USA, August 08–10, 2005). ISLPED ’05. ACM, New York, pp 387–392

  23. Tosun S (2011) Cluster-based application mapping method for network-on-chip. Adv Eng Softw 42(10):868–874

    Article  Google Scholar 

  24. Marcon CAM, Moreno EI, Calazans NLV, Moraes FG (2008) Comparison of network-on-chip mapping algorithms targeting low energy consumption. Comput Digit Tech IET 2(6):471–482

    Article  Google Scholar 

  25. Duato J, Yalamanchili S, Ni LM (2002) Interconnection networks: an engineering approach. Morgan Kaufmann

  26. Kirkpatrick S, Gelatt CD Jr, Vecchi MP (1983) Optimization by simulated annealing. Science 220(4598):671–680

  27. David EG (1989) Genetic algorithms in search, optimization, and machine learning, Addison-Wesley

  28. http://www.dashoptimization.com

  29. Chang K-C, Chen T-F (2008) Low-power algorithm for automatic topology generation for application-specific networks on chips. IET Comput Digit Tech 2(3):239–249

    Article  Google Scholar 

  30. Srinivasan K, Chatha KS, Konjevod G (2006) Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans Very Large Scale Integr Syst 14(4):407–420

    Article  Google Scholar 

  31. http://ziyang.eecs.umich.edu/dickrp/tgff/

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Acknowledgments

This work is supported by the Scientific and Technological Research Council of Turkey (TUBITAK) under Grant Number 108E233 and 112E360.

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Authors and Affiliations

  1. Computer Engineering Department, Hacettepe University, Beytepe, Ankara, Turkey

    Suleyman Tosun

  2. Computer Engineering Department, Bilkent University, Bilkent, Ankara, Turkey

    Ozcan Ozturk

  3. Computer Engineering Department, Ankara University, Golbasi, Ankara, Turkey

    Erencan Ozkan & Meltem Ozen

Authors
  1. Suleyman Tosun
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  2. Ozcan Ozturk
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  3. Erencan Ozkan
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  4. Meltem Ozen
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Correspondence to Suleyman Tosun.

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Tosun, S., Ozturk, O., Ozkan, E. et al. Application mapping algorithms for mesh-based network-on-chip architectures. J Supercomput 71, 995–1017 (2015). https://doi.org/10.1007/s11227-014-1348-x

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  • DOI: https://doi.org/10.1007/s11227-014-1348-x

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