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A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures

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Abstract

In molecular dynamics (MD) simulations, calculations of potentials and their derivatives by coordinate, i.e., forces, in a pairwise additive manner such as the Lennard–Jones interactions and a short-range part of the Coulombic interactions form the main part of arithmetic operations. It is essential to achieve high thread-level parallelization efficiency of these pairwise additive calculations of potentials and forces to use current supercomputers with many-core architectures effectively. In this paper, we propose four new thread-level parallelization algorithms for the pairwise additive potential and force calculations. We implement the four codes in a MD calculation code based on the fast multipole method. Performance benchmarks were taken on the FX100 supercomputer and Intel Xeon Phi coprocessor. The code succeeds in achieving high thread-level parallelization efficiency with 32 threads on the FX100 and up to 60 threads on the Xeon Phi.

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Acknowledgements

We thank Dr. Y. Komura for valuable suggestions to code 1. This work is supported by “Joint Usage/Research Center for Interdisciplinary Large-Scale Information Infrastructures” and “High Performance Computing Infrastructure” in Japan (Project ID jh150015-NA11, jh160040-NAJ, and jh170024-NAH). This work is also supported by the FLAGSHIP2020, MEXT within the priority study5:Development of new fundamental technologies for high-efficiency energy creation, conversion/storage and use (Proposal No. hp170241). This work is partially funded by MEXT’s program for the Development and Improvement for the Next Generation Ultra High-Speed Computer System, under its Subsidies for Operating the Specific Advanced Large Research Facilities (S. S.). Benchmark calculations were taken at the Information Technology Center (ITC) of Nagoya University, and at the ITC of The University of Tokyo. This work is also supported by JSPS KAKENHI Grant Number 16K21094 (Y. A.), and by MEXT KAKENHI Grant No. 26410012 (N. Y.).

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Authors and Affiliations

  1. Center for Computational Science, Graduate School of Engineering, Nagoya University, Nagoya, Japan

    Yoshimichi Andoh & Noriyuki Yoshii

  2. RIKEN Advanced Institute for Computational Science, Kobe, Japan

    Soichiro Suzuki

  3. Information Technology Center, The University of Tokyo, Tokyo, Japan

    Satoshi Ohshima

  4. Department of Materials Chemistry, Nagoya University, Nagoya, Japan

    Tatsuya Sakashita & Susumu Okazaki

  5. Information Technology Center, Nagoya University, Nagoya, Japan

    Masao Ogino & Takahiro Katagiri

Authors
  1. Yoshimichi Andoh
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  2. Soichiro Suzuki
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  3. Satoshi Ohshima
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  4. Tatsuya Sakashita
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  5. Masao Ogino
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  6. Takahiro Katagiri
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  7. Noriyuki Yoshii
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  8. Susumu Okazaki
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Correspondence to Yoshimichi Andoh.

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Andoh, Y., Suzuki, S., Ohshima, S. et al. A thread-level parallelization of pairwise additive potential and force calculations suitable for current many-core architectures. J Supercomput 74, 2449–2469 (2018). https://doi.org/10.1007/s11227-018-2272-2

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