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Efficient implementation of space–time adaptive processing for adaptive weights calculation based on floating point FPGAs

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Abstract

Space–time adaptive processing (STAP) has an enormous computational complexity which has confined its practical applications. In this paper, we present an implementation based on field programmable gate array (FPGA) for the most computationally intensive portion of STAP, which is the adaptive weights calculation. This involves solving a set of linear equations that uses the radar return data. In the proposed architecture, QR decomposition block is the most computationally part which is parameterized by vector size to create a trade-off between the hardware resources consumption and delay. To achieve an efficient and high-speed structure, the architecture is simulated and implemented in two cases: single-vector and multi-vector. Results show that the calculation time of weights in single-vector design is less than that of multi-vector case. The delay of weights for 6 × 8 × 120 data cube using vector size of 17 and the maximum clock frequency of 259 MHz is 139 μs, and GFLOPs/Watt is 3.89 for implementation on Arria 10 floating point FPGA. Therefore, the presented approach can realize the real-time requirement and floating point computation of the adaptive weights for STAP.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Narjes Hasanikhah & Ghafar Darvish

  2. Department of Electrical Engineering, University of Guilan, Khalij Fars Highway, Rasht, 4199613776, Iran

    Siavash Amin-Nejad

  3. Department of Electrical Engineering, Yadegar-e-Emam Branch, Islamic Azad University, Tehran, Iran

    M. R. Moniri

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  1. Narjes Hasanikhah
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  2. Siavash Amin-Nejad
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  4. M. R. Moniri
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Correspondence to Siavash Amin-Nejad.

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Hasanikhah, N., Amin-Nejad, S., Darvish, G. et al. Efficient implementation of space–time adaptive processing for adaptive weights calculation based on floating point FPGAs. J Supercomput 74, 3193–3210 (2018). https://doi.org/10.1007/s11227-018-2369-7

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  • DOI: https://doi.org/10.1007/s11227-018-2369-7

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