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Design of low-power and high-speed CNTFET-based TCAM cell for future generation networks

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Abstract

In network routers and lookup tables for fast searching, ternary content addressable memories (TCAMs) have found great use. For future generation networks, architecture is essential for efficient TCAM in terms of power consumption and speed of service. A TCAM cell with an optimized CNTFET is proposed in this paper. The TCAM cell proposed is designed for improved performance using optimized CNTFET with shorted gate (SG) CNTFET and independent gate CNTFET (IG-CNTFET). As access transistors, IG-CNTFETs are used in the SRAM cell design, and SG-CNTFETs are used in the comparison circuit. The 4 × 4 TCAM array was also planned using the TCAM cells proposed. The suggested CNTFET TCAM cell and array showed better performance than that of TCAM cells and arrays based on CMOS and FinFET. The suggested CNTFET-based TCAM with SG shows a substantial improvement in search delay and average power and peak power compared to CMOS and FinFET-based cell technology. Compared to CMOS and FinFET technologies, the average capacity of the proposed TCAM cell is substantially enhanced. The proposed technique's search delay is enhanced by 17.2 percent over TCAM cell based on FinFET. Compared to the FinFET and CMOS-based TCAM cell, the peak power of the proposed technique is also enhanced. All the simulations are carried out at 32 nm with HSPICE technology.

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  1. Department of Electronics and Communication Engineering, JNTUK, Kakinada, Andrapradesh, India

    A. Gangadhar & K. Babulu

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Gangadhar, A., Babulu, K. Design of low-power and high-speed CNTFET-based TCAM cell for future generation networks. J Supercomput 77, 10012–10022 (2021). https://doi.org/10.1007/s11227-021-03657-z

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