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Design and analysis of SRAM cell using reversible logic gates towards smart computing

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Abstract

With the enhancement of technology, the usage of electronics in various applications involving large memories for storing and processing data has increased. In this sort of application, SRAM is mainly used because of its high speed. Moreover, with the high usage of memory cells, power consumption has increased to a great extent. The current literature shows that the various parameters of SRAM, such as speed and power, need to be improved for memory cells used in object tracking applications. To improve these parameters, the architectures of SRAM must be combined with new techniques. In recent years, reversible circuits have gained extensive attention because of their low-power and low-speed characteristics. In this brief, a low-power high-speed reversible static RAM is proposed. The proposed SRAM has the combined features of data processing with low-power dissipation and high speed. The proposed architecture of SRAM yields better performance and is similar to traditional SRAM architecture in terms of delay. This paper also implements a 32 × 64 memory block for object tracking applications. This work is carried out with 45 nm CMOS technology. In the proposed design, transistors are made to operate in the weak inversion region through the use of the EKV model. The design proposed in this paper reduces garbage outputs by 60%, the quantum cost by 70%, and the quantum delay by 70% compared to the current architectures. The proposed design is simulated at different supply voltages to ensure that the power dissipation and delay of SRAM are proportional to the voltage supplied.

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Authors and Affiliations

  1. Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India

    O. Mohana chandrika & M. Siva kumar

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  1. O. Mohana chandrika
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  2. M. Siva kumar
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Correspondence to O. Mohana chandrika.

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Mohana chandrika, O., Siva kumar, M. Design and analysis of SRAM cell using reversible logic gates towards smart computing. J Supercomput 78, 2287–2306 (2022). https://doi.org/10.1007/s11227-021-03851-z

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