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Comparing the performance of multi-layer perceptron training on electrical and optical network-on-chips

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Abstract

Multi-layer perceptron (MLP) is a class of Artificial Neural Networks widely used in regression, classification, and prediction. To accelerate the training of MLP, more cores can be used for parallel computing on many-core systems. However, with the increasing number of cores integrated into the chip, the communication bottleneck in the training of MLP on electrical network-on-chip (ENoC) becomes severe, degrading MLP training performance. Replacing ENoC with optical network-on-chip (ONoC) can break the communication bottleneck in MLP training. To facilitate the development of ONoC for MLP training, it is necessary to compare and model the MLP training performance of ONoC and ENoC in advance. This paper first analyzes and compares the differences between ONoC and ENoC. Then, we formulate the performance and energy model of MLP training on ONoC and ENoC by analyzing the communication and computation time, static energy, and dynamic energy consumption, respectively. Furthermore, we conduct extensive simulations to compare their MLP training performance and energy consumption with our simulation infrastructure. The experimental results show the MLP training time of ONoC has been reduced by 65.16% and 52.51% on average in different numbers of cores and batch sizes compared with ENoC. The results also exhibit that ONoC overall has 54.86% and 43.13% on average energy reduction in different numbers of cores and batch sizes compared with ENoC. However, with a small number of cores (e.g., less than 50) in MLP training, ENoC consumes less energy than ONoC. These experiments confirm that generally ONoC is a good replacement for ENoC when using a large number of cores in terms of performance and energy consumption for MLP training.

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Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

The authors thank the reviewers for taking the time and effort necessary to review the manuscript. Besides, we acknowledge the use of New Zealand eScience Infrastructure (NeSI) high-performance computing facilities as part of this research (Project code: uoo03633).

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Authors and Affiliations

  1. Department of Computer Science, University of Otago, Dunedin, 9054, Otago, New Zealand

    Fei Dai, Yawen Chen, Zhiyi Huang, Haibo Zhang, Hao Zhang & Chengpeng Xia

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  1. Fei Dai
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Correspondence to Fei Dai.

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This study extends the work in [1], which is published at The 22nd International Conference on Parallel and Distributed Computing, Applications, and Technologies in 2022.

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Dai, F., Chen, Y., Huang, Z. et al. Comparing the performance of multi-layer perceptron training on electrical and optical network-on-chips. J Supercomput 79, 10725–10746 (2023). https://doi.org/10.1007/s11227-022-04945-y

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