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Bounding and reducing memory interference in COTS-based multi-core systems

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Abstract

In multi-core systems, main memory is a major shared resource among processor cores. A task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared main memory system. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to reduce this interference and provide an upper bound on the worst-case interference on a multi-core platform that uses a commercial-off-the-shelf (COTS) DRAM system. We explicitly model the major resources in the DRAM system, including banks, buses, and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. We find that memory interference can be significantly reduced by (i) partitioning DRAM banks, and (ii) co-locating memory-intensive tasks on the same processing core. Based on these observations, we develop a memory interference-aware task allocation algorithm for reducing memory interference. We evaluate our approach on a COTS-based multi-core platform running Linux/RK. Experimental results show that the predictions made by our approach are close to the measured worst-case interference under workloads with both high and low memory contention. In addition, our memory interference-aware task allocation algorithm provides a significant improvement in task schedulability over previous work, with as much as 96 % more tasksets being schedulable.

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Notes

  1. JEDEC. DDR3 SDRAM Standard. http://www.jedec.org.

  2. The physical structure of priority queues, bank schedulers, and the channel scheduler depends on the implementation. They can be implemented as a single hardware structure (Nesbit et al. 2006) or as multiple decoupled structures (Mutlu and Moscibroda 2007, Mutlu and Moscibroda 2008; Ausavarungnirun et al. 2012).

  3. The DRAM mapping of Fig. 1c is for the single-channel configuration in this system. Section 6 gives more details on this system.

  4. The effect of REF (\(E_{R}\)) in memory interference delay can be roughly estimated as \(E_{R}^{k+1}=\lceil \text {\{(total delay from analysis)}+E_{R}^k\}/t_{REFI}\rceil \cdot t_{RFC}\), where \(E_R^0=0\). For the DDR3-1333 with 2 Gb density below 85\(^{\circ }\), \(t_{RFC}/t_{REFI}\) is \(160\text {ns}/7.8\mu \text {s}=0.02\), so the effect of REF results in only about 2 % increase in the total memory interference delay. A more detailed analysis on REF can be found in Bhat and Mueller (2010).

  5. Micron 2Gb DDR3 Component: MT41J256M8-15E. http://download.micron.com/pdf/datasheets/dram/ddr3/2Gb_DDR3_SDRAM.pdf.

  6. OSEK/VDX OS. http://portal.osek-vdx.org/files/pdf/specs/os223.pdf.

  7. Windriver VxWorks. http://www.windriver.com.

  8. An arbitrary tie-breaking rule can be used to assign a unique priority to each task.

  9. These assumptions will be relaxed in future work.

  10. This assumption is required to bound the re-ordering effect of the memory controller, which will be described in Sect. 4.1.

  11. Note that the write-buffer draining does not completely block read requests until all the write requests are serviced. In a memory controller with write batching, read requests are always exposed to the memory controller, but write requests are exposed to and scheduled by the memory controller only when the write buffer is close to full (Lee et al. 2010). Hence, even when the write buffer is being drained, a read request can be scheduled if its commands are ready with respect to DRAM timing constraints (e.g., read and write requests to different banks).

  12. This is why the DRAM address mapping in Fig. 1c does not have a bit for channel selection.

  13. Linux/RK is available at https://rtml.ece.cmu.edu/redmine/projects/rk.

  14. McCalpin JD. STREAM: Sustainable memory bandwidth in high performance computers. http://www.cs.virginia.edu/stream.

  15. Software cache partitioning simultaneously partitions the entire physical memory space into the number of cache partitions. Therefore the spatial memory requirement of a task determines the minimum number of cache partitions for that task (Kim et al. 2013).

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Authors and Affiliations

  1. Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, USA

    Hyoseung Kim, Onur Mutlu & Ragunathan Rajkumar

  2. Software Engineering Institute, Carnegie Mellon University, Pittsburgh, USA

    Dionisio de Niz, Björn Andersson & Mark Klein

Authors
  1. Hyoseung Kim
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  2. Dionisio de Niz
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  3. Björn Andersson
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  4. Mark Klein
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  5. Onur Mutlu
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  6. Ragunathan Rajkumar
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Correspondence to Hyoseung Kim.

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This material is based upon work funded and supported by the Department of Defense under Contract No. FA8721-05-C-0003 with Carnegie Mellon University for the operation of the Software Engineering Institute, a federally funded research and development center. This material has been approved for public release and unlimited distribution. Carnegie Mellon® is registered in the U.S. Patent and Trademark Office by Carnegie Mellon University. DM-0001596.

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Kim, H., de Niz, D., Andersson, B. et al. Bounding and reducing memory interference in COTS-based multi-core systems. Real-Time Syst 52, 356–395 (2016). https://doi.org/10.1007/s11241-016-9248-1

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