Abstract
When subject to various power and substrate noise, configurable embedded memories in multimedia SoCs are importantly affected with pattern-dependant soft failures. This work investigates the effects of such failures on memory cells, arrays and circuit design. The ground bounce reduces the memory cell current more than the supply voltage drop or the substrate bias dip. A noise track-and-filter (NTAF) architecture, which is a self-timed architecture with specific layout patterns, is presented to provide the required timing relaxation, while minimizing the speed degradation. This NTAF method provides greater noise tolerance and design for manufacturing (DFM) capability. Configurable embedded SRAM and ROM in 0.18 μ m CMOS process are studied.
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Meng-Fan Chang received the B.S. degree in electrical engineering from National Cheng-Kung University in 1991. He received the M.S. degree in electrical engineering from The Pennsylvanian State University, University Park, PA, in 1996. He is currently working toward the Ph.D. degree at the Institute of Electronic Engineering, National Chiao Tung University, Hsin-Chu, Taiwan.
During 1991–1993, he joined Army of Taiwan as second lieutenant in electronic communication. From 1993 to 1994, he designed motherboards in ABIT Computer Corp., Taipei, Taiwan. During 1996–1997, he designed SRAM/ROM compilers in Mentor Graphics Corp., Warren, New Jersey. From 1997 to 2001, he designed SRAM and managed the IP Validation Program in Design Service Division (DSD) of TSMC, Hsin-Chu, Taiwan. Since 2001, he jointed Intellectual Property Library Company (IPLib), Hsin-Chu, Taiwan. He is in charge of Silicon-IP Division. He is engaged in the research and development of embedded Flash, SRAM/ROM compilers, flat-cell mask ROM and mixed-signal IPs.
His research interest included embedded memories, low-power circuit, integration issues of silicon-IP in SoC, CMOS RF and LTCC RF circuit.
Kuei Ann Wen was born in Keelung, Taiwan, R.O. China in 1961. She received the B.E.E., M.E.E. and Ph.D. degrees from the Dept. of Electrical and Computer Enginerring a National Cheng-Kung University, Taiwan, R.O. China in 1983, 1985 and 1988, respectively. She is currently a professor in the Dept. of EE at national Chiao-Tung University, Taiwan, R.O. China. At the present time, she is also involved in several research projects from Wireless Communication Consortium (http://wireless.eic.nctu.edu.tw) and Academic Center of Excellence (http://www.eic.nctu.edu.tw/ace/), which is under supervision of Dept. of Higher Education, Council of Academic Reviewer & Evaluation of R.O. China. Dr. Kuei-Ann Wen’s interests are in the areas of wireless communication system, RF circuit design, video signal processing & transmission.
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Chang, MF., Wen, KA. Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC. J VLSI Sign Process Syst Sign Image Video Technol 41, 81–91 (2005). https://doi.org/10.1007/s11265-005-6252-4
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DOI: https://doi.org/10.1007/s11265-005-6252-4