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Abstract

The Moving Picture Experts Group (MPEG) audio coding standard offers three levels of compression algorithms where the MPEG Layer III (MP3) has the best quality but with the most complexity. There are several complex coding techniques involved in MP3 audio decoding algorithm, therefore, it is difficult to make an efficient architecture design. This paper presents a hardware/software co-design method for the implementation of MP3 audio decoder, which meets the real-time requirement of MP3 standard. The software and hardware part of this decoder is partitioned into a pre-processing and a post-processing unit respectively. The pre-processing unit with a programmable parser processor is developed for the implementation of intensive decision making operations needed for audio bitstreams. The post-processing unit with a dedicated hardware of modified fast algorithm is designed for the regular and computation-intensive operations in MP3 audio decoding flow. The architecture achieves a high throughput with a reduced memory requirement and hardware complexity. With a two-level pipeline approach, it allows a high hardware utilization and is suitable to low power implementation. The proposed decoder system has been designed and implemented using VLSI cell-based approach. The die size is 3.5 × 4.45 mm2 with the maximum operation frequency of 20 MHz.

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References

  1. ISO/IEC 11172-3, Information technology—Coding of moving pictures and associated audio for digital storage media at up to 1.5 Mbits/s. Part3-Audio.

  2. W. Lau and A. Chwu, “A Common Transform Engine for MPEG & AC-3 Audio Decoder,” IEEE Transactions on Consumer Electronics, vol. 43, no. 3, 1997, pp. 559–566.

    Article  Google Scholar 

  3. Y. Jhung and S. Park, “Architecture of Dual Mode Audio Filter for AC-3 and MPEG,” IEEE Transactions on Consumer Electronics, vol. 43, no. 3, 1996, pp. 540–545.

    Google Scholar 

  4. M. Iwadare, H. Takano, Y. Shibuya, H. Sakamoto, T. Kuwajima, O. Kitabatake, and N. Kobayashi, “A Single-Chip MPEG/Audio Decoder LSI Based on a Compact Decoding Algorithm,” in VLSI Signal Processing, VIII, IEEE Signal Processing Society, 1995, pp. 118–125.

  5. S. Hong, D. Kim, and M. Song, “A Full Accuracy MPEG1 Audio Layer 3 (MP3) Decoder with Internal Data Converters,” IEEE Transactions on Consumer Electronics, vol. 45, no. 3, 1999, pp. 563–566.

    Article  Google Scholar 

  6. K.H. Bang, N.H. Jeong, J.S. Kim, Y.C. Park, and D.H. Youn, “Design and VLSI Implementation of a Digital Audio-Specific DSP Core for MP3/AAC,” IEEE Transactions on Consumer Electronics, vol. 48, no. 3, 2002, pp. 790–795.

    Article  Google Scholar 

  7. Kyu Ha Lee, Keun-Sup Lee, Tae-Hoon Hwang, Young-Cheol Park, and Dae Hee Youn, “An Architecture and Implementation of MPEG Audio Layer III Decoder Using Dual-Core DSP,” IEEE Transactions on Consumer Electronics, vol. 47, no. 4, 2001, pp. 928–933.

    Article  Google Scholar 

  8. J. Takala, J. Rostrom, T. Vaaraniemi, H. Herranen, and P. Ojala, “A Low-Power MPEG Audio Layer III Decoder IC with an Integrated Digital-to-Analog Converter,” IEEE Transactions on Consumer Electronics, vol. 46, no. 3, 2000, pp. 896–902.

    Article  Google Scholar 

  9. K. Brandenburg, G. Stoll, Y.F. Dehery, J.D. Johnston, L.V.D. Kerkhof, and E.F. Schroeder, “The ISO/MPEG Audio Codec: A Generic Standard for Coding of High Quality Digital Audio,” 92nd. AES-convention, Vienna 1992, preprint 3336.

    Google Scholar 

  10. T.H. Tsai, L.G. Chen, and Y.C. Liu, “A Novel MPEG-2 Audio Decoder with Efficient Data Arrangement and Memory Configuration,” IEEE Transactions on Consumer Electronics, vol. 43, no. 3, 1997, pp. 598–604.

    Article  Google Scholar 

  11. P. Singh, W. Moreno, N. Ranganathan, and H. Neinhaus, “A Flexible MPEG Audio Decoder Layer III Chip Architecture,” IEEE International Symposium on Circuits and Systems, vol. 4, 1998, pp. 37–40.

    Google Scholar 

  12. T. Sakamoto, M. Taruki, and T. Hase, “A Fast MPEG-Audio Layer III Algorithm for A 32-Bit MCU,” IEEE Transactions on Consumer Electronics, vol. 45, no. 3, 1999, pp. 986–993.

    Article  Google Scholar 

  13. T.H. Tsai, L.G. Chen, and R.J. Wu, “A Cost-Effective Design for MPEG2 Audio Decoder with Embedded RISC Core,” IEEE workshop on Signal Processing Systems, 1999, pp. 361–369.

  14. K. Salomonsen, S. Søgaard, and E.P. Larsen, “Design and Implementation of an MPEG/Audio Layer III Bitstream Processor,” in Department of communication technology, AALBORG University, 1997.

  15. “ARM7TM Thumb® Family Documentation,” (http://www.arm.com/techdocs.nsf/html/ARM7Docs).

  16. “ADSP2181 User Manual,” Analog Device, 1998.

  17. “TMS320VC5402 Fixed-Point Digital Signal Processor,” (http://www.ti.com).

  18. S. Li, J. Rowlands, P. Ng, M. Gillm, D.S. Toum, D. Kam, S.W., and P. Look, “An AC-3/MPEG1 Multi-Standard Audio Decoder IC,” IEEE Custom Integrated Circuit Conference, 1997, pp. 245–248.

  19. H. Sakamoto, Y. Shibuya, H. Takano, O. Kitabatake, and I. Tamoyani, “A Dolby AC-3/MPEG1 Audio Decoder Core Suitable for Audio/Visual System Integration,” in IEEE Custom Integrated Circuit Conference, 1997, pp. 241–244.

  20. G. De Michell and R.K. Gupta, “Hardware/Software Co-Design,” in Proceedings of the IEEE, vol. 85, no. 3, 1997, pp. 349–365.

    Article  Google Scholar 

  21. S.K. Jang, S.D. Kim, J. Lee, G.Y. Choi, and J.B. Ra, “Hardware-Software Co-Implementation of a H.263 Video Codec,” IEEE Transactions on Consumer Electronics, vol. 46, no. 1, 2000, pp. 191–200.

    Article  Google Scholar 

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Correspondence to Tsung-Han Tsai.

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Tsung-Han Tsai was born in Chunghua, Taiwan, R.O.C. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1990, 1994, and 1998 respectively. Dr. Tsai was an Instructor (1994–1998) and an Associate Professor (1998–1999) of the department of electrical engineering at Hwa Hsia College of Technology and Commerce. From 1999 to 2000, he was an Associate Professor of electronic engineering at Fu Jen University. Currently, he is an Assistant Professor in the department of electrical engineering at National Central University. He is also a member of IEEE and Audio Engineering Society (AES). Dr. Tsai has been awarded 8 patents and more than 70 refereed papers published in international journals and conferences. His research interests include VLSI signal processing, video/audio coding algorithms, DSP architecture design, wireless communication and System-On-Chip design.

Ya-Chau Yang was born in Tainan, ROC in 1976. He received the B.S. and M.S. degrees both in electrical engineering from Fu-Jen University in 1999 and 2001, respectively. In 2002, he was as software engineer of Foundry Access in Cadence Design Systems. Currently he is a design engineer at ActVision Technology Inc, where he works on MPEG audio decoder IP design. His interests include MPEG audio coding algorithms, VLSI signal processing/architecture and computer architecture.

Chun-Nan Liu was born in Taichung, Taiwan, R.O.C., in 1978. He received the B.S. degrees in electrical engineering from National Central University, Taiwan, in 2000. He is currently pursuing the Ph.D. degree from the Department of Electrical Engineering, National Central University, Taiwan. His area of interests are audio signal processing and VLSI signal processing.

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Tsai, TH., Yang, YC. & Liu, CN. A Hardware/Software Co-Design of MP3 Audio Decoder. J VLSI Sign Process Syst Sign Image Video Technol 41, 111–127 (2005). https://doi.org/10.1007/s11265-005-6254-2

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  • DOI: https://doi.org/10.1007/s11265-005-6254-2

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