Abstract
In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor’s expansion. This method only needs a lookup-table size of total \(n \times 2^{{n \mathord{\left/ {\vphantom {n {4 + 1}}} \right. \kern-\nulldelimiterspace} {4 + 1}}} + {\left( {n \mathord{\left/ {\vphantom {n {4 - 2}}} \right. \kern-\nulldelimiterspace} {4 - 2}} \right)} \times 2^{{n \mathord{\left/ {\vphantom {n 4}} \right. \kern-\nulldelimiterspace} 4}}\) bits, one \({\left( {n + 1} \right)} \times {3n} \mathord{\left/ {\vphantom {{3n} 4}} \right. \kern-\nulldelimiterspace} 4 - {\text{bit}}\) multiplier, one n × 3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS’s, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 μm cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.
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Chen, SG., Chih, JC. & Chou, JY. Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme. J VLSI Sign Process Syst Sign Image Video Technol 45, 153–160 (2006). https://doi.org/10.1007/s11265-006-9763-8
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DOI: https://doi.org/10.1007/s11265-006-9763-8