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An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture

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Abstract

To meet strict speed and power requirements for embedded applications, many high-end digital Signal Processors (DSPs) commonly employ non-orthogonal architectures that are typically characterized by irregular data paths, heterogeneous registers, and multiple memory banks. Obviously to harvest the benefits provided by this non-orthogonal architecture sufficient compiler support is necessary and important. However, the complexity of such architectures presents a great challenge to compiler design and the usual compilation techniques for general-purpose CPUs do not adapt well to the irregularity of DSP. The entire code generation process must include the following phases: intermediate representation, code compaction, instruction scheduling, memory bank assignment (or variable partition), and register/accumulator assignment. Much related research only considers some phases, which is inadequate. In this paper, we present an effective code generation algorithm named Rotation Scheduling with Spill Codes Predicting (RSSP) to maximally exploit the benefits of non-orthogonal architectures. It contains six parts that cover almost the entire phases of the code generation process. As well as introducing the detailed principles and algorithms of the proposed RSSP, we use an analytic model to evaluate its preliminary performance. Evaluation results clearly demonstrate the effectiveness of the proposed method. Furthermore, we also present some preliminary ideas to generalize RSSP, which can make it more practicable and suit various DSPs with similar architectural features.

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Authors and Affiliations

  1. Department of Computer Science and Information Engineering, National Chiao-Tung University, 1001 Ta Hsueh Road, Hsinchu, Taiwan, 300, People’s Republic of China

    Yi-Hsuan Lee & Cheng Chen

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  1. Yi-Hsuan Lee
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  2. Cheng Chen
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Correspondence to Cheng Chen.

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Lee, YH., Chen, C. An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture. J VLSI Sign Process Syst Sign Image Video Technol 47, 281–296 (2007). https://doi.org/10.1007/s11265-007-0053-x

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  • DOI: https://doi.org/10.1007/s11265-007-0053-x

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