Abstract
A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.
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Sansaloni, T., Pérez-Pascual, A., Torres, V. et al. Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs. J VLSI Sign Process Syst Sign Image Video Technol 47, 183–187 (2007). https://doi.org/10.1007/s11265-007-0055-8
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DOI: https://doi.org/10.1007/s11265-007-0055-8