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Configurable LDPC Decoder Architectures for Regular and Irregular Codes

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Abstract

Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3,6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths − 648,1296,1944-bits and code rates-1/2,2/3,3/4,5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.

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Acknowledgements

This work was supported in part by Nokia Corporation and by NSF under grants EIA-0321266, CCF-0541363, CNS-0551692 and CNS-0619767. We would like to thank Yang Sun for his help in ASIC synthesis. Also, we would like to thank the reviewers for their useful comments.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Rice University, 77005, Houston, TX, USA

    Marjan Karkooti, Predrag Radosavljevic & Joseph R. Cavallaro

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  1. Marjan Karkooti
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  2. Predrag Radosavljevic
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  3. Joseph R. Cavallaro
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Correspondence to Marjan Karkooti.

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Karkooti, M., Radosavljevic, P. & Cavallaro, J.R. Configurable LDPC Decoder Architectures for Regular and Irregular Codes. J Sign Process Syst Sign Image Video Technol 53, 73–88 (2008). https://doi.org/10.1007/s11265-008-0221-7

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  • DOI: https://doi.org/10.1007/s11265-008-0221-7

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