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Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories

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Abstract

This paper proposes a code placement problem, its ILP formulation, and a heuristic algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a non-cacheable memory region for an effective use of a cache memory and as a result, reduces the number of off-chip accesses. Our algorithm simultaneously finds a code layout for a cacheable region, a scratchpad region, and the other non-cacheable region of the address space so as to minimize the total energy consumption of the processor system. Experiments using a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 23% without any performance degradation compared to the best result achieved by the conventional approach.

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Acknowledgements

This work is supported by VDEC, the Univ. of Tokyo with the collaboration of Renesas Technology Corp., ROHM Co., Ltd., Toppan Printing Co., Ltd., Synopsys, Inc. and Cadence Design Systems, Inc. This work is also supported by CREST ULP program of JST and Grant-in-Aid for Scientific Research (A) 19200004.

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Authors and Affiliations

  1. Graduate School of Information Science and Electrical Engineering, Kyushu University, Motooka 744, Nishiku, Fukuoka-shi, 819-0395, Japan

    Yuriko Ishitobi

  2. System LSI Research Center, Kyushu University, Momochihama 3-8-33, Sawara-ku, Fukuoka-shi, 814-0001, Japan

    Tohru Ishihara

  3. Faculty of Information Science and Electrical Engineering, Kyushu University, Motooka 744, Nishi-ku, Fukuoka-shi, 819-0395, Japan

    Hiroto Yasuura

Authors
  1. Yuriko Ishitobi
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  2. Tohru Ishihara
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  3. Hiroto Yasuura
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Correspondence to Yuriko Ishitobi.

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Ishitobi, Y., Ishihara, T. & Yasuura, H. Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J Sign Process Syst 60, 211–224 (2010). https://doi.org/10.1007/s11265-008-0306-3

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  • DOI: https://doi.org/10.1007/s11265-008-0306-3

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