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Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding

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Abstract

This paper presents methods for efficient optimization of ASIC implementation for H.264/AVC video decoding. A systematic approach in optimization is presented in a top-down flow. Tradeoffs among Power, Throughput, and Area (PTA) at both system level and block level are studied and balanced. The system architecture is first evaluated. We then focus on the pipeline organization, parallelism, and memory architecture optimization. Different pipeline granularities are compared and their pros-and-cons are evaluated. Various parallel scenarios, especially 1 × 4-column and 4 × 1-row, are analyzed and compared. Then the detailed designs of various building blocks, such as inverse transform, inter prediction, and deblocking filter, are evaluated and their intrinsic characteristics are exploited to facilitate PTA optimization. Finally, we provide the design guidelines for ASIC implementation based on the analysis and our design experiences of five dedicated decoder chips.

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Authors and Affiliations

  1. The Chinese University of Hong Kong, Hong Kong, P.R.China

    Ke Xu & Chiu-Sing Choy

  2. National Chiao Tung University, Hsinchu, Taiwan

    Tsu-Ming Liu

  3. National Chung Cheng University, Min-Hsiung, Taiwan

    Jiun-In Guo

Authors
  1. Ke Xu
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  2. Tsu-Ming Liu
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  3. Jiun-In Guo
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  4. Chiu-Sing Choy
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Correspondence to Ke Xu.

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Xu, K., Liu, TM., Guo, JI. et al. Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding. J Sign Process Syst Sign Image Video Technol 60, 131–145 (2010). https://doi.org/10.1007/s11265-009-0408-6

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  • DOI: https://doi.org/10.1007/s11265-009-0408-6

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