Abstract
This paper presents the VLSI architecture design of pipeline sorter which is suitable for the fast sorting of the continuous serial input data stream. By decomposing the Batcher’s merge-sort process into a network of compare-and-swap (C&S) operations, two different styles of pipeline architectures based on the feedback and feed-forward data shuffling modules can be first achieved. However, both architectures suffer the low hardware utilization due to the discrepancy of input sample rate and internal processing rate. Therefore, this paper further proposes a novel digit-serial pipeline sorter architecture by dividing the data into two sub-words. In addition, the most-significant half-word data are processed first in order to reduce the internal register overhead incurred in the C&S unit. Our experimental results show that about 50% saving of gate counts can be achieved by the digit-serial approach.
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Acknowledgements
This work was supported by the National Science Council, R.O.C. under grant NSC 96-2221-E-110-041-MY3.
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Chang, YN. Digit-Serial Pipeline Sorter Architecture. J Sign Process Syst 61, 241–249 (2010). https://doi.org/10.1007/s11265-009-0444-2
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DOI: https://doi.org/10.1007/s11265-009-0444-2