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Color-Aware Instructions for Embedded Superscalar Processors

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Abstract

This paper introduces a color-aware instruction set extension that enhances the performance and efficiency in the processing of color images and video. Traditional multimedia extensions (e.g., MMX, VIS, and MDMX) depend solely on generic subword parallelism whereas the proposed color-aware instruction set (CAX) supports parallel operations on two-packed 16-bit (6:5:5) YCbCr (luminance-chrominance) values. A 16-bit YCbCr representation reduces storage requirements by 33% over the baseline 24-bit YCbCr representation while maintaining satisfactory image quality. Experimental results on an identically configured, dynamically scheduled superscalar processor indicate that CAX outperforms MDMX (a representative MIPS multimedia extension) in terms of speedup (3.9× baseline ISA with CAX versus 2.1× with MDMX) and energy reduction (75.8% reduction over baseline with CAX versus 54.8% reduction with MDMX). CAX can improve the performance and efficiency of future embedded color imaging products.

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Acknowledgements

This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MEST) (No. 2010-0010863).

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Authors and Affiliations

  1. School of Computer Engineering & Information Technology, University of Ulsan, Ulsan, South Korea, 680-749

    Jongmyon Kim

  2. Microelectronics Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, 30332-0250, USA

    Linda M. Wills & D. Scott Wills

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  1. Jongmyon Kim
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  2. Linda M. Wills
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  3. D. Scott Wills
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Correspondence to Jongmyon Kim.

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Kim, J., Wills, L.M. & Wills, D.S. Color-Aware Instructions for Embedded Superscalar Processors. J Sign Process Syst 64, 335–350 (2011). https://doi.org/10.1007/s11265-010-0497-2

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  • DOI: https://doi.org/10.1007/s11265-010-0497-2

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