Skip to main content

Advertisement

SpringerLink
Log in

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

  • Published:
Journal of Signal Processing Systems Aims and scope Submit manuscript

Abstract

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm2 area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm2/Mbps and energy efficiency of 0.55 nJ/b/iter.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22

Similar content being viewed by others

References

  1. 3GPP (2008). Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD) (25.212 V8.4.0). Dec.

  2. DVB-SH (2008). Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for satellite services to handheld devices (SH) below 3 GHz. ETSI EN 302–583 V1.1.1, March.

  3. 3GPP-LTE. Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and Channel Coding. Release 8, 3GPP TS 36.212 v8.0.0, (2007–09).

  4. IEEE 802.16e–2005 (2005). IEEE Standard for Local and Metropolitan Area Networks, Part 16: Air interface for fixed broadband wireless access systems—amendment 2: medium access control layers for combined fixed and mobile operations in licensed bands.

  5. Bougard, B., et al. (2003). A scalable 8.7 nJ/bit 75.6 Mb/s parallel concatenated convolutional (turbo-) codec. IEEE International Solid-State Circuits Conference (ISSCC), pp. 152–153, vol. 1, Feb.

  6. Thomas, C., et al. (2003). Integrated circuits for channel coding in 3G cellular mobile wireless systems. IEEE Communications Magazine, 41(8), 150–159.

    Article  Google Scholar 

  7. Lin, C.-H., Chen, C.-Y., & Wu, A.-Y. (2008). High-throughput 12-mode CTC decoder for WiMAX standard. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 216–219, April.

  8. Prescher, G., Gemmeke, T., & Noll, T. G. (2005). A parametrizable low-power high throughput turbo decoder. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 25–28, March.

  9. Kim, J. H., & Park, I. C. (2008). Duo-binary circular turbo decoder based on border metric encoding for WiMAX. Asia and South Pacific Design Automation Conference (ASPDAC), pp. 109–110, March.

  10. Wang, Z., & Parhi, K. K. (2003). High performance, high throughput turbo/SOVA decoder design. IEEE Transactions on Communications, 51(4), 570–579.

    Article  Google Scholar 

  11. Yoon, S., & Bar-Ness, Y. (2002). A parallel MAP algorithm for low latency turbo decoding. IEEE Communication Letters, 6, 288–290.

    Article  Google Scholar 

  12. Dingninou, A., Raouafi, F., & Berrou, C. (1999). Organisation de la memoire dans un turbo decodeur utilisant l’algorithm SUB-MAP. Proceedings of GRETSI, pp. 71–74, France, Sept.

  13. Bickerstaff, M., Davis, L., Thomas, C., Garret, D., & Nicol, C. (2003). A 24 Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless. IEEE International Solid-State Circuits Conference (ISSCC), pp. 150–151, vol. 1, Feb.

  14. Shin, M., & Park, I.-C. (2007). SIMD processor-based turbo decoder supporting multiple third-generation wireless standards. IEEE Transactions on VLSI, 15(7), 801–810.

    Article  Google Scholar 

  15. Asghar, R., Wu, D., Eilert, J., & Liu, D. (2010). Memory conflict analysis and implementation of a re-configurable interleaver architecture supporting unified parallel turbo decoding. Journal of Signal Processing Systems, 60(1), July. doi:10.1007/s11265-009-0394-8.

  16. Zhan, C., Arslan, T., Erdogan, A. T., & MacDougall, S. (2006). An efficient decoder scheme for double binary circular turbo codes. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 229–232, May.

  17. Sun, Y., Zhu, Y., Goel, M., & Cavallaro, J. R. (2008). Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 209–214, July.

  18. Papaharalabos, S., Sweeny, P., & Evans, B. G. (2006). Constant log-map decoding algorithm for duo-binary turbo code. IEEE Electronic Letters, 42(12), 709–710.

    Article  Google Scholar 

  19. Thul, M. J., Gilbert, R., Vogt, T., Kreiselmaier, G., & When, N. (2005). A scalable system architecture for high-throughput turbo-decoders. Journal of VLSI Signal Processing, 39, 63–77.

    Article  MATH  Google Scholar 

  20. Lee, S. J., Sanbhag, N. R., & Singer, A. C. (2005). A 285 MHz pipelined MAP decoder in 0.18 μm CMOS. IEEE Journal of Solid-State Circuits (JSSC), 40(8), 1718–1725.

    Article  Google Scholar 

  21. Kim, J. H., & Park, I. C. (2008). A 50 Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange. IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 305–308, Nov.

  22. Benkeser, C., Burg, A., Cupaiuolo, T., & Huang, Q. (2009). Design and optimization of an HSDPA turbo decoder ASIC. IEEE Journal of Solid-State Circuits (JSSC), 44(1), 98–106.

    Article  Google Scholar 

  23. Wong, C. C. et al. (2007). A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. IEEE Custom Integrated Circuits Conference (CICC), pp. 273–276, Sept.

  24. Robertson, P., Hoeher, P., & Villebrun, E. (1997). Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding. European Transaction on Telecommunication, 8(2), 119–125.

    Article  Google Scholar 

  25. Pietrobon, S. (1998). Implementation and performance of turbo/MAP decoder. International Journal of Satellite Communication, 15, 23–46.

    Article  Google Scholar 

  26. Robertson, P., Villeburn, E., & Hoeher, P. (1995). A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain. IEEE International Conference on Communications (ICC), pp. 1009–1013, June.

  27. Wang, Z., Tang, Y., & Wang, Y. (2003). Low hardware complexity parallel turbo decoder architecture. IEEE International Symposium on Circuits and System (ISCAS), pp. 53–56, May.

  28. Takeshita, O. Y., & Costello, D. J., Jr. (2000). New deterministic interleaver designs for turbo codes. IEEE Transaction for Information Theory, 46(6), 1988–2006.

    Article  MATH  Google Scholar 

Download references

Acknowledgment

This work is supported in part by the Multi-base Project from European Commission’s 7th Framework in partner with Ericson AB, Infineon Austria AG, IMEC, Lund University and KU-Leuven.

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Linköping University, Linköping, SE-58183, Sweden

    Rizwan Asghar , Di Wu , Ali Saeed , Yulin Huang  & Dake Liu

Authors
  1. Rizwan Asghar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Di Wu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ali Saeed
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Yulin Huang
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Dake Liu
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Rizwan Asghar .

Rights and permissions

Reprints and permissions

About this article

Cite this article

Asghar , R., Wu , D., Saeed , A. et al. Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support. J Sign Process Syst 66, 25–41 (2012). https://doi.org/10.1007/s11265-010-0521-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11265-010-0521-6

Keywords

Search

Navigation