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Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder

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Abstract

Viterbi decoder is a common module in communication system, which has the requirement of low power and low decoding latency. The conventional register exchange (RE) algorithm and memory-based trace-back (TB) algorithm cannot meet both constraints of power and decoding latency. In this paper, we propose a new Survivor Memory Unit (SMU) algorithm, named State Exchange (SE) algorithm. The SE algorithm uses the trace-forward unit (TFU) to run the decoding operation for low decoding latency. Besides, we enhance the SE algorithm by the concept of the trace-back (TB). Based on this enhancement, we propose two types of SE-SMU. Proposed type-I SE-SMU has lower register requirement with a long critical path. Proposed type-II SE-SMU can support the high speed requirement with the cost of additional TFUs and latency. Both two proposed SE-SMUs have the decoding latency slightly higher than the decoding latency of RE-SMU. We synthesized the proposed architecture in TSMC 0.13 um technology. Both two approaches have fewer active registers as decoding. From the power analysis, proposed SE-SMUs can give a 70% power reduction comparing with RE-SMU at 100 MHz with the decoding length = 96. The power saving ration will increase further with the longer decoding length.

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Authors and Affiliations

  1. Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, 10617, Taiwan, Republic of China

    Chun-Yuan Chu & An-Yeu Wu

  2. Department of Electrical Engineering, National Taiwan University, Taipei, 10617, Taiwan, Republic of China

    Chun-Yuan Chu & An-Yeu Wu

Authors
  1. Chun-Yuan Chu
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  2. An-Yeu Wu
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Correspondence to Chun-Yuan Chu.

Additional information

Financial supports from the SoC Technology Center (STC) at Industrial Technology Research Institute (ITRI) and NSC (grant no. NSC 96–2219- E-002-020) are greatly appreciated. The material in this paper was presented in part at the VLSI-DAT, Hsinchu, R.O.C., April 2008.

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Chu, CY., Wu, AY. Power-Efficient State Exchange Scheme for Low-Latency SMU Design of Viterbi Decoder. J Sign Process Syst 68, 233–245 (2012). https://doi.org/10.1007/s11265-011-0603-0

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  • DOI: https://doi.org/10.1007/s11265-011-0603-0

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