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Implementation of a High Throughput 3GPP Turbo Decoder on GPU

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Abstract

Turbo code is a computationally intensive channel code that is widely used in current and upcoming wireless standards. General-purpose graphics processor unit (GPGPU) is a programmable commodity processor that achieves high performance computation power by using many simple cores. In this paper, we present a 3GPP LTE compliant Turbo decoder accelerator that takes advantage of the processing power of GPU to offer fast Turbo decoding throughput. Several techniques are used to improve the performance of the decoder. To fully utilize the computational resources on GPU, our decoder can decode multiple codewords simultaneously, divide the workload for a single codeword across multiple cores, and pack multiple codewords to fit the single instruction multiple data (SIMD) instruction width. In addition, we use shared memory judiciously to enable hundreds of concurrent multiple threads while keeping frequently used data local to keep memory access fast. To improve efficiency of the decoder in the high SNR regime, we also present a low complexity early termination scheme based on average extrinsic LLR statistics. Finally, we examine how different workload partitioning choices affect the error correction performance and the decoder throughput.

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Acknowledgements

This work was supported in part by Renesas Mobile, Texas Instruments, Xilinx, and by the US National Science Foundation under grants CNS-0551692, CNS-0619767, EECS-0925942 and CNS-0923479.

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Authors and Affiliations

  1. Rice University, Houston, TX, USA

    Michael Wu, Yang Sun, Guohui Wang & Joseph R. Cavallaro

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  1. Michael Wu
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  2. Yang Sun
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  3. Guohui Wang
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  4. Joseph R. Cavallaro
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Correspondence to Michael Wu.

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Wu, M., Sun, Y., Wang, G. et al. Implementation of a High Throughput 3GPP Turbo Decoder on GPU. J Sign Process Syst 65, 171–183 (2011). https://doi.org/10.1007/s11265-011-0617-7

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  • DOI: https://doi.org/10.1007/s11265-011-0617-7

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