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Distributed Arithmetic based Split-Radix FFT

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Abstract

In this paper we have designed a Split-radix type FFT unit without using multipliers. All the complex multiplications required for this type of FFT are implemented using Distributed Arithmetic (DA) technique. A method is incorporated to overcome the result overflow problem introduced by DA method. Proposed FFT architecture is implemented in 180 nm CMOS technology at a supply voltage of 1.8 V.

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References

  1. Berkeman, A., Öwall, V., Torkelson, M. (2000). A low logic depth complex multiplier using distributed arithmetic. IEEE Journal of Solid-State Circuits, 35, 656–659.

    Article  Google Scholar 

  2. Perez-Pascual, A., Sanaloni, T., Valls, J. (2002). FPGA-based radix-4 butterflies for HIPERLAN/2. In IEEE international symposium on circuits and systems (pp. 277–280). Scottsdale.

  3. Chang, Y.N., & Parhi, K.K. (2000). High-performance digit-serial complex multiplier. IEEE Transactions on Circuits and Systems, 47, 570–572.

    Article  Google Scholar 

  4. Chen, T., Sunanda, T.G., Jin, J. (1999). COBRA: a 100-MOPS single-chip programmable and expandable FFT. IEEE Transactions Very Large Scale Integrative (VLSI) Systems, 7, 174–182.

    Article  Google Scholar 

  5. Fan, C.-P., Lee, M.-S., Su, G.-A. (2006). A low multiplier and multiplication cost 256-point FFT implementation with simplified radix-16 SDF architecture. In IEEE asia pacific conference on circuits and systems (pp. 1935–1938).

  6. Cooley, J., & Tukey, J. (1965). An algorithm for the machine calculation of complex fourier series. Mathematical Comparative, 19, 297–301.

    Article  MATH  MathSciNet  Google Scholar 

  7. Duhamel, P., & Hollmann, H. (1985). Implementation of split-radix FFT algorithms for complex, real and real-symmetric data. IEEE International Conference on Acoustics, Speech and Signal Processing, 10, 784–787.

    Article  Google Scholar 

  8. Duhamel, P., & Hollmann, H. (1984). Split radix FFT algorithm. Electronics Letters, 20, 14–16.

    Article  Google Scholar 

  9. Good, I. (1958). The interaction algorithm and practical fourier analysis. Journal of the Royal Statistical Society, B-20, 361–372.

    MathSciNet  Google Scholar 

  10. Xiao, H., Pan, A., Chen, Y., Zeng, X. (2008). Low-cost reconfigurable VLSI architecture for fast fourier transform. IEEE Transactions on Consumer Electronics, 54, 1617–1622.

    Article  Google Scholar 

  11. He, S., & Torkelson, T. (1995). A pipelined bit-serial complex multiplier using distributed arithmetic. International Symposium on Circuits and Systems, 3, 2313–2316.

    Article  Google Scholar 

  12. Jiang, R.M. (2007). An area-efficient FFT architecture for OFDM digital video broadcasting. IEEE Transactions on Consumer Electronics, 53, 1322–1326.

    Article  Google Scholar 

  13. Kolba, D., & Parks, T. (1977). A prime factor algorithm using high-speed convolution. IEEE Transaction Acoustics Speech Signal Process, ASSP-25, 281–294.

    Article  Google Scholar 

  14. Maharatna, G., & Jagdhold, U. (2004). A 64-point fourier transform chip for high-speed wireless LAN application using OFDM. IEEE Journal Solid-State Circuits, 39, 484–493.

    Article  Google Scholar 

  15. Morris, L. (1978). A comparative study of time efficient FFT and WFTA programs for general purpose computers. IEEE Transaction Acoustics Speech Signal Process, ASSP-26, 141–150.

    Article  Google Scholar 

  16. Engels, M., Eberle, W., Gyselinckx, B. (1998). Design of a 100 Mbps wireless local area network. In Proceedings IEEE URSI international symposium signals and systems (pp. 253–256).

  17. Jiang, M., Yang, B., Huang, R., Zhang, T.Y., Wang, Y.Y. (2007). Multiplierless fast fourier transform architecture. Electronics Letters, 43, 191-192.

    Article  Google Scholar 

  18. Karlsson, M., Vesterbacka, M., Wanhammar, L. (1997). Design and implementation of a complex multiplier using distributed arithmetic (pp. 222–231).

  19. Nawab, H., & McClellan, J. (1979). Bounds on the minimum number of data transfers in WFTA and FFT programs. IEEE Transaction Acoustics Speech Signal Process, ASSP-27, 394–398.

    Article  Google Scholar 

  20. van Nee, R., & Prasad, R. (2000). OFDM for wireless multimedia communications. Norwell: Archtech House.

    Google Scholar 

  21. Peled, A., & Liu, B. (1973). A new approach to the realization of nonrecursive digital filters. IEEE Transaction Audio and Electroacoustics, 21, 477–485.

    Article  Google Scholar 

  22. Chow, P., Vranesic, Z., Yen, J.L. (1983). A pipelined distributed srithmetic PFFT processor. IEEE Transactions on Computers, 32, 198–206.

    Google Scholar 

  23. Shaditalab, M., Bois, G., Sawan, M. (1998). Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks. In IEEE symposium on FPGAs for custom computing machines (pp. 137–138).

  24. Siu, W., & Chen, C. (1983). New realization technique of high-speed discrete fourier transform described by distributed arithmetic. IEE Proceedings, 130, 177–181.

    Google Scholar 

  25. Weste, N., & Skellern, D.J. (1998). VLSI for OFDM. IEEE Communication Magazine, 36, 127–131.

    Article  Google Scholar 

  26. White, S.A. (1989). Applications of distributed arithmetic to digital signal processing: a tutorial review. IEEE ASSP Magazine, 6, 4–19.

    Article  Google Scholar 

  27. Winograd, S. (1976). On computing the discrete fourier transform. Proceedings of the National Academy of Sciences of the United States of America, 73, 1005–1006.

    Article  MATH  MathSciNet  Google Scholar 

  28. Hui, W., Ding, T., McCanny, V. (1996). A 64-point fourier transform chip for video motion compensation using phase correlation. IEEE Journal of Solid-State Circuits, 31, 1751–1761.

    Article  Google Scholar 

  29. Li, X., Lai, Z., Cui, J. (2007). A low power and small area FFT processor for OFDM demodulator. IEEE Transactions on Consumer Electronics, 53, 274–277.

    Article  MATH  Google Scholar 

  30. Yeh, W.C., & Jen, C.W. (2003). High-speed and low-power split-radix FFT. IEEE Transactions on Signal Processing, 51, 864–874.

    Article  MathSciNet  Google Scholar 

  31. Lin, Y.T., Tsai, P.Y., Chiueh, T.D. (2005). Low-power variable-length fast fourier transform processor. IEEE Proceedings Computers and Digital Techniques, 152, 499–506.

    Article  Google Scholar 

  32. Zohar, S. (1973). The counting recursive digital filter. IEEE Transaction on Computers, C-22, 338–347.

    Article  Google Scholar 

  33. Zohar, S. (1973). New hardware realization of nonrecursive digital filters. IEEE Transaction on Computers, C-22, 328–338.

    Article  Google Scholar 

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Acknowledgments

This work is carried out using the Synopsys and the Cadence tools provided by the SMDP II project at IIT Guwahati.

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Authors and Affiliations

  1. EEE Department, IIT Guwahati, Guwahati, Assam, India

    Sunil P. Joshi & Roy Paily

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  1. Sunil P. Joshi
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  2. Roy Paily
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Correspondence to Roy Paily.

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Joshi, S.P., Paily, R. Distributed Arithmetic based Split-Radix FFT. J Sign Process Syst 75, 85–92 (2014). https://doi.org/10.1007/s11265-013-0790-y

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