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A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec

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Abstract

Motion vector (MV) prediction and residue coding technique is adopted to fully utilize the motion field redundancy in the prevailing video standards, and MV prediction is desired in both video encoder and decoder. The computation burden for MV prediction is not very high. However, there is high irregularity in raw MV prediction algorithm with two-stage and four-level hierarchical tree control flows. It makes efficient VLSI architecture implementation challenging. The high irregularity is mainly derived from the abundant inter prediction modes including variable block size partition and temporal prediction direction, as well as the irregular control flow of the MV prediction algorithm. This paper proposes a highly regular architecture to implement MV prediction for multi-standard video codec. Complex control logic is simplified by regularly table look-up of the control parameters predefined and stored in on-chip tables. The parameters of the current macroblock (MB) and its neighboring blocks are initialized and refreshed in a regular manner. Moreover, pipelining and parallelism are employed in the proposed architecture to improve throughput efficiency and tradeoff between hardware cost and efficiency. Simulation results verify the effectiveness of the proposed design.

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Acknowledgments

This work was supported by ZJNSF Y1110114, NSFC 60802025 and 61001108, S&T project of Zhejiang province 2010C310075, the open project of State Key Laboratory of ASIC & System of Fudan University 10KF010, and the open project of SKL of Novel Soft Technology, Nanjing University (KFKT2012B09).

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Authors and Affiliations

  1. China Jiliang University, Hangzhou, China

    Haibing Yin & Shizhong Li

  2. The University of Chinese Academy Sciences, Beijing, China

    Honggang Qi

  3. Hangzhou Silan Microelectronic Inc, Hangzhou, China

    Hongqi Hu

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  1. Haibing Yin
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  2. Shizhong Li
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  3. Honggang Qi
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  4. Hongqi Hu
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Correspondence to Haibing Yin.

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Yin, H., Li, S., Qi, H. et al. A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec. J Sign Process Syst 76, 47–62 (2014). https://doi.org/10.1007/s11265-013-0808-5

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  • DOI: https://doi.org/10.1007/s11265-013-0808-5

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