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Enhancing Hardware Assisted Test Insertion Capabilities on Embedded Processors using an FPGA-based Agile Test Support Co-processor

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Abstract

With software defects reducing profits in many fields, it is worthwhile to consider moving key defect reducing strategies from one development area into another. However, inadequate tool support has compromised attempts to transfer Agile methodology’s successes from “business systems” to embedded system development. We outline the advantages of adding an Agile test support (ATS) co-processor to provide low overhead hardware-assisted test insertion capabilities into testing frameworks for test-first (Agile) and test-last hardware-software design philosophies. We propose the development of an ATS FPGA co-processor using an extension to the eXtreme Programming Inspired (XPI) embedded lifecycle. The performance of a prototype ATS co-processor is compared to the existing instruction watch (low overhead) and data watch (high overhead) debug hardware present on Analog Devices ADSP-BF5XX Blackfin processors.

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Acknowledgment

This work was financed through an industrial collaborative research and development (CRD) grant co-sponsored by Analog Devices and the Natural Sciences and Engineering Research Council (NSERC) of Canada. Thanks to S. Choudhury (Calgary, Canada) for assistance in preparing the manuscript.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada, T2N 1 N4

    Michael Smith & Dongcheng Deng

  2. Department of Electrical Engineering and Computer Science, York University, Ontario, Canada, M3J 1P3

    Syed Islam

  3. Department of Electrical and Computer, University of Alberta, Edmonton, Alberta, Canada, T6G 2V4

    James Miller

Authors
  1. Michael Smith
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  2. Dongcheng Deng
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  3. Syed Islam
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  4. James Miller
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Correspondence to Michael Smith.

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Smith, M., Deng, D., Islam, S. et al. Enhancing Hardware Assisted Test Insertion Capabilities on Embedded Processors using an FPGA-based Agile Test Support Co-processor. J Sign Process Syst 79, 285–298 (2015). https://doi.org/10.1007/s11265-013-0845-0

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