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Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications

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Abstract

Aggressive power supply voltage V d d scaling is widely utilized to exploit the design margin introduced by the process, voltage and environment variations. However, scaling beyond the critical V d d results to numerous setup timing errors, and hence to an unacceptable output quality. In this paper, we propose computation-skip (CS) scheme to mitigate setup timing errors, for recursive digital signal processors with a fixed cycles per instruction (CPI). A coordinate rotation digital computer (CORDIC) with the proposed CS scheme still functions when scaling beyond the error-free voltage. It enables better-than-worst-case design constraint and achieves 1.82 X energy saving w.r.t. nominal V d d condition, another 1.49 X energy saving without quality degradation, and another 1.09 X energy saving when sacrificing 8.35 dB output quality.

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Authors and Affiliations

  1. imec, Kapeldreef 75, 3001, Heverlee, Belgium

    Yanxiang Huang, Meng Li, Chunshu Li & Peter Debacker

  2. KU Leuven, ESAT, Kasteelpark Arenberg 10, 3001, Heverlee, Belgium

    Yanxiang Huang, Chunshu Li & Liesbet Van der Perre

Authors
  1. Yanxiang Huang
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  2. Meng Li
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  3. Chunshu Li
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  4. Peter Debacker
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  5. Liesbet Van der Perre
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Correspondence to Yanxiang Huang.

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Huang, Y., Li, M., Li, C. et al. Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications. J Sign Process Syst 84, 413–424 (2016). https://doi.org/10.1007/s11265-015-1096-z

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  • DOI: https://doi.org/10.1007/s11265-015-1096-z

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